ADC_CTRL Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.470s	6.065ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.430s	764.262us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.000s	487.798us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.021m	26.172ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.910s	866.901us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.300s	531.783us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.000s	487.798us	20	20	100.00
		adc_ctrl_csr_aliasing	5.910s	866.901us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	22.872m	496.937ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.320m	495.454ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.384m	494.771ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.401m	486.584ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.424m	599.956ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	22.597m	416.210ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.268m	497.463ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	23.392m	496.696ms	34	50	68.00
V2	poweron_counter	adc_ctrl_poweron_counter	19.970s	4.826ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.574m	44.480ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.121m	136.734ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.299m	661.923ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.750s	513.101us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.900s	508.379us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.850s	592.782us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.850s	592.782us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.430s	764.262us	5	5	100.00
		adc_ctrl_csr_rw	4.000s	487.798us	20	20	100.00
		adc_ctrl_csr_aliasing	5.910s	866.901us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.900s	4.823ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.430s	764.262us	5	5	100.00
		adc_ctrl_csr_rw	4.000s	487.798us	20	20	100.00
		adc_ctrl_csr_aliasing	5.910s	866.901us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.900s	4.823ms	20	20	100.00
V2		TOTAL			720	740	97.30
V2S	tl_intg_err	adc_ctrl_sec_cm	18.030s	8.167ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.720s	8.355ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.720s	8.355ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	27.986m	10.000s	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			897	920	97.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.11	96.45	100.00	100.00	99.01	98.06	91.21

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
- Test adc_ctrl_clock_gating has 10 failures.
  - 3.adc_ctrl_clock_gating.101781093672607981174027855172355074121910005689334204096924920414388074518341
    Line 151, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.adc_ctrl_clock_gating.40101834416765829410962634919687073975025177746114391956765560993646062576169
    Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.adc_ctrl_stress_all_with_rand_reset.30937118468647219481367790563811251047692779701409167455508439507862491315761
    Line 166, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_filters_both has 1 failures.
  - 26.adc_ctrl_filters_both.56805448846580937347612422382472814415362732620245447603519185266537316395239
    Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test adc_ctrl_clock_gating has 5 failures.

1.adc_ctrl_clock_gating.7663552689220447779924018000670759192521980288964395049274233140201340925871
Line 185, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 436239700758 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 436239700758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.adc_ctrl_clock_gating.16280322112018321209333806831019060941062350741935508587048466263882210773887
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 4327215160 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 4327215160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

10.adc_ctrl_stress_all_with_rand_reset.32762833318530133080986659483928450596865631003426834353943842560889507338999
Line 177, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6230443214 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 6230443214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.adc_ctrl_stress_all_with_rand_reset.50836803591668852803546984646345232271258692971156922920729132721802412534516
Line 219, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 59014759999 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 59014759999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_both has 2 failures.

19.adc_ctrl_filters_both.23164451560940596363182230105105548691384926437850205040630409377449047679446
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 521209763901 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 521209763901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.adc_ctrl_filters_both.55014009022662558092012612419953700360415530980629171631409007755484606955420
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 247139180178 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 247139180178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 1 failures.

38.adc_ctrl_filters_interrupt.98508736592871086107757815930554248876011891421051248747624085345141287641737
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 163144361182 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 163144361182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 1 failures.

48.adc_ctrl_clock_gating.64194844157520068932247746289850967482116606107538073484670458079163990477649
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 80303545088 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 80303545088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---