AES/MASKED Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	93.985us	1	1	100.00
V1	smoke	aes_smoke	9.000s	767.190us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	55.617us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	105.595us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	9.254ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	129.598us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	175.046us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	105.595us	20	20	100.00
		aes_csr_aliasing	6.000s	129.598us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	767.190us	50	50	100.00
		aes_config_error	10.000s	579.094us	50	50	100.00
		aes_stress	9.000s	203.013us	50	50	100.00
V2	key_length	aes_smoke	9.000s	767.190us	50	50	100.00
		aes_config_error	10.000s	579.094us	50	50	100.00
		aes_stress	9.000s	203.013us	50	50	100.00
V2	back2back	aes_stress	9.000s	203.013us	50	50	100.00
		aes_b2b	23.000s	372.830us	50	50	100.00
V2	backpressure	aes_stress	9.000s	203.013us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	767.190us	50	50	100.00
		aes_config_error	10.000s	579.094us	50	50	100.00
		aes_stress	9.000s	203.013us	50	50	100.00
		aes_alert_reset	11.000s	464.343us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	456.243us	50	50	100.00
		aes_config_error	10.000s	579.094us	50	50	100.00
		aes_alert_reset	11.000s	464.343us	50	50	100.00
V2	trigger_clear_test	aes_clear	17.000s	766.885us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	1.292ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	464.343us	50	50	100.00
V2	stress	aes_stress	9.000s	203.013us	50	50	100.00
V2	sideload	aes_stress	9.000s	203.013us	50	50	100.00
		aes_sideload	10.000s	371.932us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	2.191ms	50	50	100.00
V2	stress_all	aes_stress_all	52.000s	1.076ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	67.387us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	1.242ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	1.242ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	55.617us	5	5	100.00
		aes_csr_rw	5.000s	105.595us	20	20	100.00
		aes_csr_aliasing	6.000s	129.598us	5	5	100.00
		aes_same_csr_outstanding	5.000s	90.334us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	55.617us	5	5	100.00
		aes_csr_rw	5.000s	105.595us	20	20	100.00
		aes_csr_aliasing	6.000s	129.598us	5	5	100.00
		aes_same_csr_outstanding	5.000s	90.334us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	178.817us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	133.464us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	133.464us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	133.464us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	133.464us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	469.783us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	536.235us	5	5	100.00
		aes_tl_intg_err	7.000s	1.927ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.927ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	464.343us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	133.464us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	767.190us	50	50	100.00
		aes_stress	9.000s	203.013us	50	50	100.00
		aes_alert_reset	11.000s	464.343us	50	50	100.00
		aes_core_fi	20.000s	10.010ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	133.464us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	64.251us	50	50	100.00
		aes_stress	9.000s	203.013us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	203.013us	50	50	100.00
		aes_sideload	10.000s	371.932us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	64.251us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	64.251us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	64.251us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	64.251us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	64.251us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	203.013us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	203.013us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	1.585ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
		aes_ctr_fi	6.000s	68.263us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	1.585ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.003ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	1.585ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_ctr_fi	6.000s	68.263us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
		aes_ctr_fi	6.000s	68.263us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	464.343us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
		aes_ctr_fi	6.000s	68.263us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
		aes_ctr_fi	6.000s	68.263us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_ctr_fi	6.000s	68.263us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	1.585ms	50	50	100.00
		aes_control_fi	39.000s	10.012ms	285	300	95.00
		aes_cipher_fi	44.000s	10.003ms	336	350	96.00
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	28.000s	4.014ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	98.63	96.52	99.44	95.68	98.07	97.78	98.96	98.79

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 15.aes_cipher_fi.90045755742827078606792689289222787083990863227616285096731396445300082442432
    Line 146, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003213807 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003213807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.aes_cipher_fi.16979134120914224960658424707697323972775886285730184150839344327881946351501
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002682839 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002682839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 8 failures.
  - 54.aes_control_fi.35546035353386543269959415524292129047420417009573300160941625357225346525600
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 97.aes_control_fi.69917222866133979519384626492091966180161914689322170259837329944021582913823
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 1 failures.
  - 260.aes_cipher_fi.112543376869436880631932196438198944714794256223845758409760781904122396502768
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/260.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 63.aes_control_fi.89045378168426394737938076956239363156062012021394282649403425421935200603154
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021579148 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021579148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 99.aes_control_fi.22590286170839475411985218396614902174287883773220644082878040816629724912037
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/99.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010052345 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010052345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.59653672088015562573376058685738539789494392822184602376902130717926688621672
Line 189, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 272128203 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 272128203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.24803712681987833027680870239812457208069222964873330808385520878662451687077
Line 723, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3622168837 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3622168837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.12195690487982401226513380396398963505857423654121010639763873642754657552194
    Line 246, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 770607788 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 770607788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.107242749130946212741054164700829091712529047697887458852896682390724467815282
    Line 267, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4014408500 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4014408500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.91820079753664110834785336295189651436317900161363984739959975064116937556380
    Line 442, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 719345962 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 719345962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.101051774207405278418453320810847815163191309676319662862080108466617767564565
    Line 192, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  23199169 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  23199169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 15.aes_core_fi.101140679270011369534500728688402806537369389776381054646690026851675415268314
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10026735239 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026735239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.aes_core_fi.100540859928345588098698665057485480137499029525016830625020104651893963103609
    Line 134, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009520660 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009520660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```