AES/UNMASKED Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	70.559us	1	1	100.00
V1	smoke	aes_smoke	7.000s	348.999us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	103.643us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	108.538us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	189.360us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	525.337us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	83.530us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	108.538us	20	20	100.00
		aes_csr_aliasing	7.000s	525.337us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	348.999us	50	50	100.00
		aes_config_error	7.000s	179.348us	50	50	100.00
		aes_stress	8.000s	514.874us	50	50	100.00
V2	key_length	aes_smoke	7.000s	348.999us	50	50	100.00
		aes_config_error	7.000s	179.348us	50	50	100.00
		aes_stress	8.000s	514.874us	50	50	100.00
V2	back2back	aes_stress	8.000s	514.874us	50	50	100.00
		aes_b2b	11.000s	209.138us	50	50	100.00
V2	backpressure	aes_stress	8.000s	514.874us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	348.999us	50	50	100.00
		aes_config_error	7.000s	179.348us	50	50	100.00
		aes_stress	8.000s	514.874us	50	50	100.00
		aes_alert_reset	7.000s	405.900us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	58.113us	50	50	100.00
		aes_config_error	7.000s	179.348us	50	50	100.00
		aes_alert_reset	7.000s	405.900us	50	50	100.00
V2	trigger_clear_test	aes_clear	11.000s	80.855us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	831.747us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	405.900us	50	50	100.00
V2	stress	aes_stress	8.000s	514.874us	50	50	100.00
V2	sideload	aes_stress	8.000s	514.874us	50	50	100.00
		aes_sideload	7.000s	130.937us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	97.916us	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	1.234ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	79.974us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	42.000s	82.331us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	42.000s	82.331us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	103.643us	5	5	100.00
		aes_csr_rw	6.000s	108.538us	20	20	100.00
		aes_csr_aliasing	7.000s	525.337us	5	5	100.00
		aes_same_csr_outstanding	7.000s	1.567ms	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	103.643us	5	5	100.00
		aes_csr_rw	6.000s	108.538us	20	20	100.00
		aes_csr_aliasing	7.000s	525.337us	5	5	100.00
		aes_same_csr_outstanding	7.000s	1.567ms	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	395.157us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	87.581us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	87.581us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	87.581us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	87.581us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	148.908us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.457ms	5	5	100.00
		aes_tl_intg_err	35.000s	465.082us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	35.000s	465.082us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	405.900us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	87.581us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	348.999us	50	50	100.00
		aes_stress	8.000s	514.874us	50	50	100.00
		aes_alert_reset	7.000s	405.900us	50	50	100.00
		aes_core_fi	40.000s	10.015ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	87.581us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	73.373us	50	50	100.00
		aes_stress	8.000s	514.874us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	514.874us	50	50	100.00
		aes_sideload	7.000s	130.937us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	73.373us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	73.373us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	73.373us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	73.373us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	73.373us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	514.874us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	514.874us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	605.437us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
		aes_ctr_fi	10.000s	51.647us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	605.437us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	36.000s	10.042ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	605.437us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_ctr_fi	10.000s	51.647us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
		aes_ctr_fi	10.000s	51.647us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	405.900us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
		aes_ctr_fi	10.000s	51.647us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
		aes_ctr_fi	10.000s	51.647us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_ctr_fi	10.000s	51.647us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	605.437us	49	50	98.00
		aes_control_fi	33.000s	10.002ms	277	300	92.33
		aes_cipher_fi	36.000s	10.042ms	324	350	92.57
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	24.000s	2.351ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.30	97.66	94.72	98.80	93.60	98.07	91.11	98.65	97.59

Failure Buckets

Job timed out after * minutes has 21 failures:
- Test aes_cipher_fi has 9 failures.
  - 0.aes_cipher_fi.47808816637472538724350996888542188939102490312667487545637434698874526986262
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 4.aes_cipher_fi.49771016450474318194889327192609990394188937965205426390729811811875058390758
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_control_fi has 12 failures.
  - 12.aes_control_fi.57043978477071006082038691263502479034245963138856827221897871871068712801624
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 152.aes_control_fi.82040011902224961450971880123672168501802884494092262117066677318567061595372
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/152.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 17 failures:
- Test aes_cipher_fi has 17 failures.
  - 43.aes_cipher_fi.76217862111094817511587410180778117987549788968607913426641827753425528807954
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010476515 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010476515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 76.aes_cipher_fi.100478487042473595782804558589535260472452735086952452013549661708966745696993
    Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008132565 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008132565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 9.aes_control_fi.70111240849433426914056138006969382895551137485684014513605259557797735901317
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10001782232 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001782232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 87.aes_control_fi.7922085393412913757187250772209742936812612198187805947499718687398124508025
    Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/87.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002352254 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002352254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.86015577753133702997991718390050663506015091652127802873334471079878979470197
Line 214, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1706276893 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1706276893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.66075539329942035865512940721102153002199609145355130424756368444086588418199
Line 1370, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2350722664 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2350722664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

4.aes_stress_all_with_rand_reset.36099701437061439897763350551709889518883307895241806850561686741750028566137
Line 548, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 505110975 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 505070975 PS)
  UVM_ERROR @ 505110975 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 505110975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

44.aes_fi.77149413274400044699691105011453311890268085454076993517985816319944889503317
Line 3934, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/44.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 41515731 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 41475731 PS)
  UVM_ERROR @  41515731 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  41515731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 51.aes_core_fi.87751718896432593283536759791352974693691359113225686931905684091618298887309
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021039995 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021039995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 64.aes_core_fi.110686006452478716353220104916007985038467286538205527290717501137900108697891
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015287049 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015287049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.49261276922716303657875188778348444541768678396237578551317560768591179542381
    Line 595, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 994284250 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 994284250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```