CSRNG Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	234.667us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	23.620us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	47.273us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	16.000s	606.228us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	187.004us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	218.592us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	47.273us	20	20	100.00
		csrng_csr_aliasing	8.000s	187.004us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	1.188ms	199	200	99.50
V2	alerts	csrng_alert	1.167m	6.070ms	500	500	100.00
V2	err	csrng_err	11.000s	21.981us	500	500	100.00
V2	cmds	csrng_cmds	8.400m	43.495ms	50	50	100.00
V2	life cycle	csrng_cmds	8.400m	43.495ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.417m	67.245ms	50	50	100.00
V2	intr_test	csrng_intr_test	6.000s	133.655us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	189.299us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.486ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.486ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	23.620us	5	5	100.00
		csrng_csr_rw	6.000s	47.273us	20	20	100.00
		csrng_csr_aliasing	8.000s	187.004us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	732.719us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	23.620us	5	5	100.00
		csrng_csr_rw	6.000s	47.273us	20	20	100.00
		csrng_csr_aliasing	8.000s	187.004us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	732.719us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	8.000s	255.659us	5	5	100.00
		csrng_tl_intg_err	12.000s	887.179us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	175.404us	50	50	100.00
		csrng_csr_rw	6.000s	47.273us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.167m	6.070ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.417m	67.245ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.167m	6.070ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.417m	67.245ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.167m	6.070ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	887.179us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
		csrng_sec_cm	8.000s	255.659us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	1.188ms	199	200	99.50
		csrng_err	11.000s	21.981us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.167m	1.097ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1619	1630	99.33

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.79	98.63	96.69	99.97	97.48	92.08	100.00	97.36	90.82

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:

  • Test csrng_stress_all_with_rand_reset has 9 failures.

    • 1.csrng_stress_all_with_rand_reset.105906937690392705548687193904990168039316792359090459757796521135297757468668
      Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 188751227 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 188751227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.csrng_stress_all_with_rand_reset.107036133741460638059866263739863440003407424511610932509844482035569072640030
      Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 116384274 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 116384274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.100474994838734833495286587690833578329937243379230245567948486970937688266445
      Line 110, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  23473033 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
        UVM_INFO @  23473033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

  • Test csrng_intr has 1 failures.

    • 131.csrng_intr.14916130132739406516330465775025707199167396512543450102036928011776345198949
      Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/131.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 403568833 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @ 403568833 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @ 403568833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---