EDN Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.590s 27.999us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.570s 18.203us 5 5 100.00
V1 csr_rw edn_csr_rw 2.490s 56.999us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.780s 287.877us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 3.230s 203.931us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.030s 24.854us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.490s 56.999us 20 20 100.00
edn_csr_aliasing 3.230s 203.931us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.019m 2.675ms 300 300 100.00
V2 csrng_commands edn_genbits 1.019m 2.675ms 300 300 100.00
V2 genbits edn_genbits 1.019m 2.675ms 300 300 100.00
V2 interrupts edn_intr 2.780s 23.012us 50 50 100.00
V2 alerts edn_alert 2.940s 50.591us 200 200 100.00
V2 errs edn_err 2.810s 24.750us 100 100 100.00
V2 disable edn_disable 2.460s 22.282us 50 50 100.00
edn_disable_auto_req_mode 2.990s 44.620us 50 50 100.00
V2 stress_all edn_stress_all 8.550s 328.823us 50 50 100.00
V2 intr_test edn_intr_test 2.480s 13.889us 50 50 100.00
V2 alert_test edn_alert_test 3.130s 112.033us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.670s 447.505us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.670s 447.505us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.570s 18.203us 5 5 100.00
edn_csr_rw 2.490s 56.999us 20 20 100.00
edn_csr_aliasing 3.230s 203.931us 5 5 100.00
edn_same_csr_outstanding 2.970s 36.780us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.570s 18.203us 5 5 100.00
edn_csr_rw 2.490s 56.999us 20 20 100.00
edn_csr_aliasing 3.230s 203.931us 5 5 100.00
edn_same_csr_outstanding 2.970s 36.780us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.220s 1.071ms 5 5 100.00
edn_tl_intg_err 4.020s 127.877us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.560s 17.197us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.940s 50.591us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.220s 1.071ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.220s 1.071ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.220s 1.071ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.220s 1.071ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.940s 50.591us 200 200 100.00
edn_sec_cm 9.220s 1.071ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.940s 50.591us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.020s 127.877us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.714m 22.036ms 23 50 46.00
V3 TOTAL 23 50 46.00
TOTAL 1103 1130 97.61

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.79 98.32 94.23 97.02 91.86 96.36 99.78 92.94

Failure Buckets