ENTROPY_SRC Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 104.338us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 58.705us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 255.865us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 800.381us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.040ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 45.152us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 255.865us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.040ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 104.338us 50 50 100.00
entropy_src_rng 8.383m 17.762ms 18 300 6.00
entropy_src_fw_ov 8.350m 16.054ms 177 300 59.00
V2 firmware_mode entropy_src_fw_ov 8.350m 16.054ms 177 300 59.00
V2 rng_mode entropy_src_rng 8.383m 17.762ms 18 300 6.00
V2 rng_max_rate entropy_src_rng_max_rate 11.067m 15.606ms 7 400 1.75
V2 health_checks entropy_src_rng 8.383m 17.762ms 18 300 6.00
V2 conditioning entropy_src_rng 8.383m 17.762ms 18 300 6.00
V2 interrupts entropy_src_rng 8.383m 17.762ms 18 300 6.00
entropy_src_intr 22.000s 1.033ms 50 50 100.00
V2 alerts entropy_src_rng 8.383m 17.762ms 18 300 6.00
entropy_src_functional_alerts 8.000s 424.374us 50 50 100.00
V2 stress_all entropy_src_stress_all 2.135h 10.000s 47 50 94.00
V2 functional_errors entropy_src_functional_errors 9.233m 10.012ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 31.000s 351.498us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 238.264us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 71.230us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 304.887us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 304.887us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 58.705us 5 5 100.00
entropy_src_csr_rw 5.000s 255.865us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.040ms 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 272.640us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 58.705us 5 5 100.00
entropy_src_csr_rw 5.000s 255.865us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.040ms 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 272.640us 20 20 100.00
V2 TOTAL 1504 2340 64.27
V2S tl_intg_err entropy_src_sec_cm 5.000s 623.578us 5 5 100.00
entropy_src_tl_intg_err 8.000s 692.234us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 8.383m 17.762ms 18 300 6.00
entropy_src_cfg_regwen 6.000s 36.621us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 8.383m 17.762ms 18 300 6.00
V2S sec_cm_config_redun entropy_src_rng 8.383m 17.762ms 18 300 6.00
V2S sec_cm_intersig_mubi entropy_src_rng 8.383m 17.762ms 18 300 6.00
entropy_src_fw_ov 8.350m 16.054ms 177 300 59.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.233m 10.012ms 965 1000 96.50
entropy_src_sec_cm 5.000s 623.578us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.233m 10.012ms 965 1000 96.50
entropy_src_sec_cm 5.000s 623.578us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 8.383m 17.762ms 18 300 6.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.233m 10.012ms 965 1000 96.50
entropy_src_sec_cm 5.000s 623.578us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.233m 10.012ms 965 1000 96.50
entropy_src_sec_cm 5.000s 623.578us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.233m 10.012ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 8.000s 424.374us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 8.000s 692.234us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.800m 12.088ms 7 50 14.00
V3 TOTAL 7 50 14.00
TOTAL 1691 2570 65.80

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.01 98.13 95.28 98.33 95.37 96.56 96.88 90.68 86.14

Failure Buckets