HMAC Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.090s	1.240ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.220s	56.629us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.420s	54.729us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.570s	1.278ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.290s	471.541us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	19.115m	110.240ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.420s	54.729us	20	20	100.00
		hmac_csr_aliasing	8.290s	471.541us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	52.320s	4.775ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.960m	7.897ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.868m	104.889ms	30	30	100.00
		hmac_test_sha384_vectors	9.485m	96.994ms	75	75	100.00
		hmac_test_sha512_vectors	9.282m	15.333ms	75	75	100.00
		hmac_test_hmac256_vectors	16.010s	688.177us	50	50	100.00
		hmac_test_hmac384_vectors	17.070s	415.717us	60	60	100.00
		hmac_test_hmac512_vectors	20.680s	425.930us	75	75	100.00
V2	burst_wr	hmac_burst_wr	47.390s	12.209ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	20.718m	88.800ms	10	10	100.00
V2	error	hmac_error	1.451m	9.625ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.617m	9.359ms	10	10	100.00
V2	save_and_restore	hmac_smoke	17.090s	1.240ms	10	10	100.00
		hmac_long_msg	52.320s	4.775ms	10	10	100.00
		hmac_back_pressure	1.960m	7.897ms	25	25	100.00
		hmac_datapath_stress	20.718m	88.800ms	10	10	100.00
		hmac_burst_wr	47.390s	12.209ms	50	50	100.00
		hmac_stress_all	39.494m	510.907ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.090s	1.240ms	10	10	100.00
		hmac_long_msg	52.320s	4.775ms	10	10	100.00
		hmac_back_pressure	1.960m	7.897ms	25	25	100.00
		hmac_datapath_stress	20.718m	88.800ms	10	10	100.00
		hmac_wipe_secret	1.617m	9.359ms	10	10	100.00
		hmac_test_sha256_vectors	4.868m	104.889ms	30	30	100.00
		hmac_test_sha384_vectors	9.485m	96.994ms	75	75	100.00
		hmac_test_sha512_vectors	9.282m	15.333ms	75	75	100.00
		hmac_test_hmac256_vectors	16.010s	688.177us	50	50	100.00
		hmac_test_hmac384_vectors	17.070s	415.717us	60	60	100.00
		hmac_test_hmac512_vectors	20.680s	425.930us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.090s	1.240ms	10	10	100.00
		hmac_long_msg	52.320s	4.775ms	10	10	100.00
		hmac_back_pressure	1.960m	7.897ms	25	25	100.00
		hmac_datapath_stress	20.718m	88.800ms	10	10	100.00
		hmac_burst_wr	47.390s	12.209ms	50	50	100.00
		hmac_error	1.451m	9.625ms	10	10	100.00
		hmac_wipe_secret	1.617m	9.359ms	10	10	100.00
		hmac_test_sha256_vectors	4.868m	104.889ms	30	30	100.00
		hmac_test_sha384_vectors	9.485m	96.994ms	75	75	100.00
		hmac_test_sha512_vectors	9.282m	15.333ms	75	75	100.00
		hmac_test_hmac256_vectors	16.010s	688.177us	50	50	100.00
		hmac_test_hmac384_vectors	17.070s	415.717us	60	60	100.00
		hmac_test_hmac512_vectors	20.680s	425.930us	75	75	100.00
		hmac_stress_all	39.494m	510.907ms	50	50	100.00
V2	stress_all	hmac_stress_all	39.494m	510.907ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.160s	124.149us	50	50	100.00
V2	intr_test	hmac_intr_test	2.190s	17.891us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.600s	998.093us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.600s	998.093us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.220s	56.629us	5	5	100.00
		hmac_csr_rw	2.420s	54.729us	20	20	100.00
		hmac_csr_aliasing	8.290s	471.541us	5	5	100.00
		hmac_same_csr_outstanding	4.020s	283.758us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.220s	56.629us	5	5	100.00
		hmac_csr_rw	2.420s	54.729us	20	20	100.00
		hmac_csr_aliasing	8.290s	471.541us	5	5	100.00
		hmac_same_csr_outstanding	4.020s	283.758us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.680s	366.638us	5	5	100.00
		hmac_tl_intg_err	6.180s	883.770us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.180s	883.770us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.090s	1.240ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.100s	142.226us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.191m	91.741ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.240s	10.201us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.96	99.84	97.25	100.00	100.00	99.84	99.52	47.30