I2C Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.693m	14.635ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	54.230s	1.651ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.390s	30.263us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.380s	63.241us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.900s	706.344us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.770s	137.653us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.720s	152.675us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.380s	63.241us	20	20	100.00
		i2c_csr_aliasing	2.770s	137.653us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	11.460s	839.504us	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	50.998m	76.942ms	17	50	34.00
V2	host_maxperf	i2c_host_perf	36.940m	50.297ms	48	50	96.00
V2	host_override	i2c_host_override	2.280s	26.120us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.427m	4.526ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.401m	2.303ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.980s	643.748us	50	50	100.00
		i2c_host_fifo_fmt_empty	21.680s	503.611us	50	50	100.00
		i2c_host_fifo_reset_rx	13.960s	959.913us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.700m	16.548ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	43.280s	4.522ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.970s	493.291us	20	50	40.00
V2	target_glitch	i2c_target_glitch	17.690s	10.977ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	20.504m	74.228ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	9.670s	4.437ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.454m	7.750ms	50	50	100.00
		i2c_target_intr_smoke	11.260s	1.446ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.220s	252.038us	50	50	100.00
		i2c_target_fifo_reset_tx	3.360s	244.731us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	12.965m	52.686ms	50	50	100.00
		i2c_target_stress_rd	1.454m	7.750ms	50	50	100.00
		i2c_target_intr_stress_wr	5.308m	19.406ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.280s	1.223ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.260m	2.980ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	9.770s	1.312ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	39.250s	10.146ms	24	50	48.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.450s	648.821us	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.290s	175.968us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	36.940m	50.297ms	48	50	96.00
		i2c_host_perf_precise	14.631m	24.258ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	43.280s	4.522ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	12.500s	1.149ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.420s	2.952ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.170s	1.850ms	50	50	100.00
		i2c_target_nack_txstretch	3.360s	149.418us	36	50	72.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	22.280s	660.366us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.720s	792.000us	50	50	100.00
V2	alert_test	i2c_alert_test	2.290s	19.795us	50	50	100.00
V2	intr_test	i2c_intr_test	2.420s	24.623us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.270s	95.234us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.270s	95.234us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.390s	30.263us	5	5	100.00
		i2c_csr_rw	2.380s	63.241us	20	20	100.00
		i2c_csr_aliasing	2.770s	137.653us	5	5	100.00
		i2c_same_csr_outstanding	2.800s	218.672us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.390s	30.263us	5	5	100.00
		i2c_csr_rw	2.380s	63.241us	20	20	100.00
		i2c_csr_aliasing	2.770s	137.653us	5	5	100.00
		i2c_same_csr_outstanding	2.800s	218.672us	20	20	100.00
V2		TOTAL			1674	1792	93.42
V2S	tl_intg_err	i2c_tl_intg_err	3.560s	90.880us	20	20	100.00
		i2c_sec_cm	2.630s	128.037us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.560s	90.880us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	34.690s	950.730us	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.714m	10.688ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	28.440s	4.122ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1854	2042	90.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.98	97.26	89.70	74.17	72.02	94.20	98.52	89.96

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 39 failures:

Test i2c_host_stress_all has 28 failures.

0.i2c_host_stress_all.1768034517836897007278602575354603610145738587038148000473230061786600493580
Line 155, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 78909853628 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10750886

2.i2c_host_stress_all.98331115219078752509756822068537677108148952492093248684895539031345613986700
Line 170, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 76941509896 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @98037918

... and 26 more failures.

Test i2c_host_mode_toggle has 11 failures.

2.i2c_host_mode_toggle.110284803809493765952608250678168054901453351367941855731762003806692437583704
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 493291323 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @112553

5.i2c_host_mode_toggle.111521354802385824470019804130205875601868502492654691220378495443472883154191
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 155426780 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11079

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 33 failures:
- Test i2c_target_unexp_stop has 32 failures.
  - 1.i2c_target_unexp_stop.83986154583690078250221268068219111404648480505016007054610356689186729861815
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  64985591 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 217 [0xd9])
  UVM_INFO @  64985591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.8683470111374044939926945618097576441240329276291313768958975811426993779685
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  30372739 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 9 [0x9])
  UVM_INFO @  30372739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 30 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.63580970165956789053023175698324665801392253592381856880891670490260506687018
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34734140 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 113 [0x71])
  UVM_INFO @  34734140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
- Test i2c_target_hrst has 26 failures.
  - 2.i2c_target_hrst.95017480812623887113294630259682381176465619033336548569767716337983552068853
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10492257510 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10492257510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_hrst.101736801174453042194390881569649979733197599563097464262838213826849574796884
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10639659298 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10639659298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.31770343904631798113642014661460998066110279141172414867023860586613162612722
Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 950729869 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 950729869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.27245151496965714775352605102835866627426302099023748570151797150347783986499
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5169463141 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5169463141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 9 failures.

0.i2c_target_stress_all_with_rand_reset.109383900335808763597794443768446369787098101359919018075786099980463644010685
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2000601781 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2000601781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.12831910817797432705213317410800405797934482809402556670580949087839708016947
Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4032325173 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4032325173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
- Test i2c_target_nack_txstretch has 14 failures.
  - 1.i2c_target_nack_txstretch.29247344398914739752044679621632770898701204826348925827818741724633954279898
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 278862913 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 278862913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_nack_txstretch.333610149943587057388104609859838289296358349632342365041861852606070917090
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 221437877 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 221437877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 13 failures.

0.i2c_host_mode_toggle.102145041224395126627610887412043104170882584297062721732906579678262887808710
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 188611439 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

1.i2c_host_mode_toggle.83691394246776787446285977018734438258894854035520464737954388620704698043502
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  84124423 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 11 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 12 failures:
- Test i2c_target_unexp_stop has 12 failures.
  - 0.i2c_target_unexp_stop.74182823251021599773271200619398982943179379272149490253408220217230547744487
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 206361880 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 206361880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_unexp_stop.77906881777787568071291624946524991969446819771549442182645115900760756076994
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 109019588 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 109019588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
- Test i2c_target_stretch has 6 failures.
  - 1.i2c_target_stretch.22707263951703902081046777023417036457917982479224797434224089408309480709570
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10023942637 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10023942637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_stretch.106278181363602548404232974806638549152056110788419032670341938390928151990185
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10223731680 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10223731680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:

Test i2c_target_unexp_stop has 5 failures.

3.i2c_target_unexp_stop.35340972111081130316115475462751499160579191396150064776355182329698063439435
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 516713787 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 516713787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_unexp_stop.77236941076808449937638033399444924044316643335142048200669055786795298605045
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 826696288 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 826696288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
- Test i2c_host_mode_toggle has 5 failures.
  - 7.i2c_host_mode_toggle.61250027693405292431825714120724133762024340219674709906406030484209704216591
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 163356266 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x2759a194, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 163356266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_host_mode_toggle.90148692056582485938832330218955072274183911202778862560597731727206232355252
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 156131338 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xd515be14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 156131338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Job timed out after * minutes has 4 failures:
- Test i2c_host_stress_all has 2 failures.
  - 7.i2c_host_stress_all.99531163571673715878056024283475313368667182744725154949354595052998203899459
    Log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 46.i2c_host_stress_all.12386444812073362862566008325051445450394471668608600376269260598103316423614
    Log /nightly/runs/scratch/master/i2c-sim-vcs/46.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_perf has 1 failures.
  - 16.i2c_host_perf.104707003256472616056108586800491142126015910049431614060659775859227002400926
    Log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_error_intr has 1 failures.
  - 26.i2c_host_error_intr.55779858846821524433975908088741361622532026808093980605430527124056269824716
    Log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_error_intr/latest/run.log
```
  Job timed out after 60 minutes
```
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 35.i2c_target_tx_stretch_ctrl.93253628403612387764221825195515225767109449834630225251546376848295458164017
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 37.i2c_target_tx_stretch_ctrl.94807659279489722530739168175519910470469591320401892977880012046147832665559
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 43.i2c_target_fifo_watermarks_tx.98758093154730206315896413258633859954300036712446030274650921292467637271082
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

1.i2c_host_stress_all.101950680515783634534089668880184788143146927593913824406338301863921482413613
Line 231, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 36627311288 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9551096

33.i2c_host_stress_all.19580089619384290590373054770690715416307941041380634368923813848504821602581
Line 207, in log /nightly/runs/scratch/master/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 71342699821 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7469074

... and 1 more failures.

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all has 2 failures.
  - 1.i2c_target_stress_all.77098525411244804907945315875814143250240214469071817030619079976190853138056
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 34229230683 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 34229230683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.i2c_target_stress_all.82584271764090930499719304935658232248899817528450488331945556386691404544064
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 32698005932 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 32698005932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_unexp_stop has 1 failures.
  - 13.i2c_target_unexp_stop.48964229617586317494411700639125438887430335751710379624198622664994923756608
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 10687839004 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 10687839004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 10.i2c_host_perf.41471770271930591807176188793595215792175792351265433828290338867303279647556
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 16.i2c_host_mode_toggle.113488050906574944552363031135726910751173428165177729119045741730103913211425
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```