KEYMGR Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	18.550s	927.513us	50	50	100.00
V1	random	keymgr_random	37.300s	10.729ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.460s	31.627us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.510s	22.453us	16	20	80.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.080s	1.128ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	7.780s	727.809us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.060s	94.259us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.510s	22.453us	16	20	80.00
		keymgr_csr_aliasing	7.780s	727.809us	4	5	80.00
V1		TOTAL			146	155	94.19
V2	cfgen_during_op	keymgr_cfg_regwen	41.980s	4.617ms	48	50	96.00
V2	sideload	keymgr_sideload	38.370s	3.407ms	50	50	100.00
		keymgr_sideload_kmac	39.380s	1.738ms	50	50	100.00
		keymgr_sideload_aes	29.330s	5.967ms	50	50	100.00
		keymgr_sideload_otbn	40.170s	1.674ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	38.790s	5.971ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	10.760s	281.150us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.070s	1.710ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	47.340s	8.415ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	50.660s	4.493ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	25.490s	4.727ms	50	50	100.00
V2	stress_all	keymgr_stress_all	3.417m	15.555ms	48	50	96.00
V2	intr_test	keymgr_intr_test	2.090s	22.514us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.580s	57.965us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.980s	1.187ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.980s	1.187ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.460s	31.627us	5	5	100.00
		keymgr_csr_rw	2.510s	22.453us	16	20	80.00
		keymgr_csr_aliasing	7.780s	727.809us	4	5	80.00
		keymgr_same_csr_outstanding	3.300s	92.348us	13	20	65.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.460s	31.627us	5	5	100.00
		keymgr_csr_rw	2.510s	22.453us	16	20	80.00
		keymgr_csr_aliasing	7.780s	727.809us	4	5	80.00
		keymgr_same_csr_outstanding	3.300s	92.348us	13	20	65.00
V2		TOTAL			728	740	98.38
V2S	sec_cm_additional_check	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
		keymgr_tl_intg_err	8.130s	1.398ms	15	20	75.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.600s	187.745us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.600s	187.745us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.600s	187.745us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.600s	187.745us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.990s	484.324us	12	20	60.00
V2S	prim_count_check	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.130s	1.398ms	15	20	75.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.600s	187.745us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	41.980s	4.617ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.300s	10.729ms	50	50	100.00
		keymgr_csr_rw	2.510s	22.453us	16	20	80.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.300s	10.729ms	50	50	100.00
		keymgr_csr_rw	2.510s	22.453us	16	20	80.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.300s	10.729ms	50	50	100.00
		keymgr_csr_rw	2.510s	22.453us	16	20	80.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	10.760s	281.150us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	50.660s	4.493ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	50.660s	4.493ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.300s	10.729ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.810s	1.143ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	42.530s	7.431ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	10.760s	281.150us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	42.530s	7.431ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	42.530s	7.431ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	42.530s	7.431ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.620s	2.602ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	42.530s	7.431ms	50	50	100.00
V2S		TOTAL			152	165	92.12
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	19.340s	2.342ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1052	1110	94.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.10	98.07	98.37	100.00	99.02	98.63	91.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 29 failures:

Test keymgr_tl_intg_err has 5 failures.

0.keymgr_tl_intg_err.8819218963223042931003998952718594008053619727947308862784263960483440691426
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  20692390 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  20692390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.45258084504467383415986561989920262049195952949817579943707310190147349600760
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  74212236 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  74212236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_aliasing has 1 failures.

1.keymgr_csr_aliasing.42672748899354985382499149083412942109380878440137527087451609230509079146903
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  77140855 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  77140855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_bit_bash has 1 failures.

2.keymgr_csr_bit_bash.36252620557934140221316390664572652194667096096242246633641916572642351260209
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 1127967141 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 1127967141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 7 failures.

4.keymgr_same_csr_outstanding.11629669349513729592257253043406472899179166411295953592583472251719981787527
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  23100354 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  23100354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_same_csr_outstanding.4810574152958953034480303183275924269705571540021331813605678302388540863638
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 143490020 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 143490020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 8 failures.

5.keymgr_shadow_reg_errors_with_csr_rw.12456866723317086998750744282266603324864525050030320552030738919135614584287
Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 191254974 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 191254974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_shadow_reg_errors_with_csr_rw.80993244842759728477164114766663273560138996363019646003328426484601594797248
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  34801332 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  34801332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 1.keymgr_stress_all_with_rand_reset.29020211829449101171562827287738380348032217986581258671269727708465529139511
    Line 380, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1159418619 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1159418619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.91707150860223310355855040210488147031042701760309184525759263687732917872856
    Line 153, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 485212114 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 485212114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 1 failures.

11.keymgr_stress_all.57820150820200826479913575407551163038639461020675868048262975153608935511892
Line 281, in log /nightly/runs/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all/latest/run.log

  UVM_ERROR @  67520864 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  67520864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_otbn has 1 failures.

26.keymgr_sideload_otbn.115421472837538309649015558874406581944066357672964892641844592624740989516526
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest/run.log

  UVM_ERROR @   3258217 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   3258217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

48.keymgr_cfg_regwen.37529396761369754321923552895978427783167843512868052694564733520566553719738
Line 510, in log /nightly/runs/scratch/master/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @ 117126206 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 117126206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 12.keymgr_cfg_regwen.72402864535164140597272025216829320682745421143800738983669885262236719375526
    Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @  13628122 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @  13628122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 48.keymgr_stress_all.24580501903094400373885883114715702858864936515270537515234614242781516163525
    Line 3402, in log /nightly/runs/scratch/master/keymgr-sim-vcs/48.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3710546364 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3282887504 [0xc3ace350] vs 3282887504 [0xc3ace350]) reg name: keymgr_reg_block.sw_share0_output_6
  UVM_INFO @ 3710546364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```