KMAC/MASKED Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.665m	12.457ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.220s	112.011us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.500s	55.468us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.540s	6.874ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.680s	938.397us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.290s	88.432us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.500s	55.468us	20	20	100.00
		kmac_csr_aliasing	8.680s	938.397us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.140s	13.865us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.850s	19.939us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.042h	134.358ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.535m	29.193ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.970m	761.692ms	5	5	100.00
		kmac_test_vectors_sha3_256	30.895m	59.640ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.894m	58.107ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.988m	167.754ms	5	5	100.00
		kmac_test_vectors_shake_128	40.253m	227.890ms	5	5	100.00
		kmac_test_vectors_shake_256	37.544m	320.420ms	5	5	100.00
		kmac_test_vectors_kmac	4.830s	112.517us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.220s	317.338us	5	5	100.00
V2	sideload	kmac_sideload	8.240m	87.097ms	50	50	100.00
V2	app	kmac_app	6.546m	32.179ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.088m	88.066ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.502m	81.820ms	50	50	100.00
V2	error	kmac_error	7.982m	41.141ms	50	50	100.00
V2	key_error	kmac_key_error	21.550s	11.897ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.400s	419.987us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.070s	576.274us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	59.500s	2.608ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.492m	34.396ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	58.790s	3.695ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.778m	103.580ms	49	50	98.00
V2	intr_test	kmac_intr_test	2.370s	38.304us	50	50	100.00
V2	alert_test	kmac_alert_test	2.390s	47.479us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.260s	696.970us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.260s	696.970us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.220s	112.011us	5	5	100.00
		kmac_csr_rw	2.500s	55.468us	20	20	100.00
		kmac_csr_aliasing	8.680s	938.397us	5	5	100.00
		kmac_same_csr_outstanding	3.420s	127.644us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.220s	112.011us	5	5	100.00
		kmac_csr_rw	2.500s	55.468us	20	20	100.00
		kmac_csr_aliasing	8.680s	938.397us	5	5	100.00
		kmac_same_csr_outstanding	3.420s	127.644us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.820s	129.596us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.820s	129.596us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.820s	129.596us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.820s	129.596us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.790s	687.883us	11	20	55.00
V2S	tl_intg_err	kmac_sec_cm	1.407m	56.485ms	5	5	100.00
		kmac_tl_intg_err	4.910s	331.409us	14	20	70.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.910s	331.409us	14	20	70.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	58.790s	3.695ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.665m	12.457ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.240m	87.097ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.820s	129.596us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.407m	56.485ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.407m	56.485ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.407m	56.485ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.665m	12.457ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	58.790s	3.695ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.407m	56.485ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.800m	18.635ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.665m	12.457ms	50	50	100.00
V2S		TOTAL			60	75	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.721m	5.248ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			917	940	97.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.16	99.09	94.43	99.89	78.87	97.05	99.06	97.72

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_tl_intg_err has 6 failures.

0.kmac_tl_intg_err.73568049971942365906792577413637192112853508706379522852111918237623774828415
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  20424302 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  20424302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_tl_intg_err.12170781661018632973902244289147950691701040220654397437680531107894958325708
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  10050172 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  10050172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

1.kmac_shadow_reg_errors_with_csr_rw.57479263464017726205743053285494644030520219356684377300073976491430287392306
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  64774805 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  64774805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.88837826766617309838982389122422946969982629653018408873384389059056368559088
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  11519483 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  11519483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.6611087320732774820929369020500697752975696085309353425245563069388476205769
    Line 213, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9533144870 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9533144870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.51264467896131651944617115332758235037338255031527659754030197450001966224788
    Line 183, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19718336237 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 19718336237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 2 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.
  - 0.kmac_shadow_reg_errors_with_csr_rw.39789036588081039540665236400397883786889475795848246859018156256140001922153
    Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 239431447 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (677304653 [0x285ed94d] vs 4195289698 [0xfa0f0a62]) Regname: kmac_reg_block.prefix_8 reset value: 0x0
  UVM_INFO @ 239431447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_shadow_reg_errors_with_csr_rw.102204426010864157823384434101778760484682058384250209606066960513603718391752
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  24842437 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3601051771 [0xd6a3b07b] vs 0 [0x0]) Regname: kmac_reg_block.prefix_0 reset value: 0x0
  UVM_INFO @  24842437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 3.kmac_burst_write.68100420434949036461734075887108982394340505379639947442319745387754960952313
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_burst_write/latest/run.log
```
  UVM_ERROR @  73013838 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  73013838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 49.kmac_stress_all.109765221656626567389122172447141248491580230232260101445165475910004196969325
    Line 86, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 517370953 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 517370953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 3.kmac_shadow_reg_errors_with_csr_rw.75084130484937599553844315692579891477611419325394284166017034302816259299747
    Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 116559783 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1390729876 [0x52e4da94] vs 3882111156 [0xe76450b4]) Regname: kmac_reg_block.prefix_9.prefix_0 reset value: 0x0
  UVM_INFO @ 116559783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```