KMAC/UNMASKED Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.158m	21.759ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.520s	85.108us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.670s	121.614us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.770s	3.995ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.990s	144.938us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.890s	159.180us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.670s	121.614us	20	20	100.00
		kmac_csr_aliasing	8.990s	144.938us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.140s	11.954us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.060s	385.510us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.373m	526.320ms	50	50	100.00
V2	burst_write	kmac_burst_write	17.197m	141.218ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.236m	188.960ms	5	5	100.00
		kmac_test_vectors_sha3_256	29.394m	183.229ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.147m	298.353ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.651m	31.823ms	5	5	100.00
		kmac_test_vectors_shake_128	29.974m	68.441ms	5	5	100.00
		kmac_test_vectors_shake_256	5.269m	23.094ms	5	5	100.00
		kmac_test_vectors_kmac	4.220s	563.677us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.150s	305.186us	5	5	100.00
V2	sideload	kmac_sideload	7.457m	76.944ms	50	50	100.00
V2	app	kmac_app	4.553m	25.377ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.011m	16.687ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.508m	134.063ms	50	50	100.00
V2	error	kmac_error	6.619m	15.586ms	50	50	100.00
V2	key_error	kmac_key_error	15.160s	6.649ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	2.492m	10.067ms	37	50	74.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.020s	1.033ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.370s	3.193ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.030m	5.997ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	19.110s	869.708us	50	50	100.00
V2	stress_all	kmac_stress_all	35.223m	474.619ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.320s	18.071us	50	50	100.00
V2	alert_test	kmac_alert_test	2.370s	48.689us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.110s	541.646us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.110s	541.646us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.520s	85.108us	5	5	100.00
		kmac_csr_rw	2.670s	121.614us	20	20	100.00
		kmac_csr_aliasing	8.990s	144.938us	5	5	100.00
		kmac_same_csr_outstanding	3.760s	488.356us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.520s	85.108us	5	5	100.00
		kmac_csr_rw	2.670s	121.614us	20	20	100.00
		kmac_csr_aliasing	8.990s	144.938us	5	5	100.00
		kmac_same_csr_outstanding	3.760s	488.356us	20	20	100.00
V2		TOTAL			726	740	98.11
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.170s	567.109us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.170s	567.109us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.170s	567.109us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.170s	567.109us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.620s	767.401us	14	20	70.00
V2S	tl_intg_err	kmac_sec_cm	1.058m	12.888ms	5	5	100.00
		kmac_tl_intg_err	5.510s	387.478us	12	20	60.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.510s	387.478us	12	20	60.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	19.110s	869.708us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.158m	21.759ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.457m	76.944ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.170s	567.109us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.058m	12.888ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.058m	12.888ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.058m	12.888ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.158m	21.759ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	19.110s	869.708us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.058m	12.888ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.740m	27.224ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.158m	21.759ms	50	50	100.00
V2S		TOTAL			61	75	81.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.940m	31.616ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			904	940	96.17

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.74	97.18	94.38	100.00	73.55	95.93	99.02	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

0.kmac_shadow_reg_errors_with_csr_rw.103447476423794916614045252956815804720266401318444696648048245231951603836233
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  13759497 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  13759497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.31041644973798323964839614132511996834566736787342157123471448397804043773175
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  76252876 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  76252876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_tl_intg_err has 8 failures.

1.kmac_tl_intg_err.32498798417558792069090985929770410864086405936464616620197879253484518438259
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @   8123820 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @   8123820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_tl_intg_err.63578699814507753288296609679081181746177837194066320306308571750731851110954
Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @ 101821634 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @ 101821634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 1.kmac_stress_all_with_rand_reset.26408387964898353829077991115967248077200542025068801291695449718201564967527
    Line 182, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7846250784 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7846250784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.95342206045905020135087566896207003713486401562998989540769723720732727927781
    Line 275, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31615834685 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 31615834685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 8.kmac_sideload_invalid.66205158841091823188143482125985264801139597358439977645652272920380548079100
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10242140636 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x671de000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10242140636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.kmac_sideload_invalid.24377432057427444765708486719283845606908087057326737444448527156322995531509
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10066932802 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7eef2000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10066932802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 30.kmac_sideload_invalid.42901051086203386053490300344678399746898876679258323898146745390519861441930
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10021199120 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1ab4f000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10021199120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.kmac_sideload_invalid.18417031834236919319333152274682568526360517553061479252663412197629139703838
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10017185275 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x94e9d000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10017185275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 9.kmac_sideload_invalid.4641289443403925687287184555080615521552403320763966698671275470857097183104
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10244471628 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9fac3000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10244471628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.kmac_sideload_invalid.100588330392964480811196670021058448323331885785174695152896842495074992641510
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10061223553 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6b918000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10061223553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.93950630789599496075848179959552367612534885344795477087364146416855758979447
    Line 197, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5539631743 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5539631743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 6.kmac_key_error.11677729236337047193088256957885914319356771803935644742625099818978280029746
    Line 88, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1534005954 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1534005954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 7.kmac_sideload_invalid.6745303764990049791032809072104782982623844838083422566831740389976544015017
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10023580777 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdcfe2000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10023580777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.68979765490504912468640841410861087133903663610213597896783078684871138174195
    Line 109, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10319288377 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbcce4000, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
  UVM_INFO @ 10319288377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 28.kmac_sideload_invalid.36386134593944383126770082349554608751407644373891354481674852752751521564284
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10071396197 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6a99a000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10071396197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 31.kmac_sideload_invalid.31096055228579390843523773230987783150817244246495961824188388945801768686255
    Line 92, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10574663867 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc7d3a000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10574663867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 44.kmac_sideload_invalid.50060433501173767007601964724153217871801980407804729387484749384279760812246
    Line 92, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10516595551 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaabd8000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
  UVM_INFO @ 10516595551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```