OTBN Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	40.070us	1	1	100.00
V1	single_binary	otbn_single	44.000s	139.579us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	13.000s	117.732us	5	5	100.00
V1	csr_rw	otbn_csr_rw	13.000s	30.198us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	476.277us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	28.773us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	41.630us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	13.000s	30.198us	20	20	100.00
		otbn_csr_aliasing	8.000s	28.773us	5	5	100.00
V1	mem_walk	otbn_mem_walk	42.000s	3.462ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	33.000s	375.443us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	35.000s	88.111us	10	10	100.00
V2	multi_error	otbn_multi_err	2.883m	544.321us	1	1	100.00
V2	back_to_back	otbn_multi	1.167m	1.006ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.250m	1.930ms	10	10	100.00
V2	lc_escalation	otbn_escalate	34.000s	392.224us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	71.925us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	44.824us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	24.665us	50	50	100.00
V2	intr_test	otbn_intr_test	30.000s	15.854us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	41.000s	86.178us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	41.000s	86.178us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	13.000s	117.732us	5	5	100.00
		otbn_csr_rw	13.000s	30.198us	20	20	100.00
		otbn_csr_aliasing	8.000s	28.773us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	34.006us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	13.000s	117.732us	5	5	100.00
		otbn_csr_rw	13.000s	30.198us	20	20	100.00
		otbn_csr_aliasing	8.000s	28.773us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	34.006us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	14.000s	96.409us	10	10	100.00
		otbn_dmem_err	20.000s	53.465us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	64.364us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	73.804us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	64.130us	5	5	100.00
		otbn_urnd_err	11.000s	18.577us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	19.621us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	29.400us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	29.498us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
		otbn_tl_intg_err	1.650m	492.296us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.300m	163.474us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	40.070us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	20.000s	53.465us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	96.409us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.650m	492.296us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	34.000s	392.224us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	96.409us	10	10	100.00
		otbn_dmem_err	20.000s	53.465us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	71.925us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	19.621us	5	5	100.00
		otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	96.409us	10	10	100.00
		otbn_dmem_err	20.000s	53.465us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	71.925us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	19.621us	5	5	100.00
		otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	34.000s	392.224us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	96.409us	10	10	100.00
		otbn_dmem_err	20.000s	53.465us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	71.925us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	19.621us	5	5	100.00
		otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	308.535us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	24.212us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	55.000s	503.825us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	55.000s	503.825us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	19.754us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	454.639us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	128.175us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	128.175us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	57.000s	701.854us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.167m	1.006ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	24.048us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	44.000s	139.579us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.250m	1.185ms	1	5	20.00
V2S		TOTAL			153	163	93.87
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.100m	7.130ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			571	585	97.61

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.12	99.64	96.06	99.73	93.22	93.73	100.00	97.95	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

0.otbn_sec_cm.8566993527595901362112694226841869589573714183810913592359174215125412861521
Line 100, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 26445138 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 26445138 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  26445138 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  26445138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_cm.114792233603399792793204843257201228420155476346202851984767608529506006813916
Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 44828273 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 44828273 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  44828273 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  44828273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 2 failures.

1.otbn_sec_wipe_err.108544561815767503497097782408828849560625865144647921359388342007373687092279
Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19347181 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19347181 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19347181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.41506290287892806864505954043344310415327917655454035294927308236886473115016
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 701853570 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 701853570 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 701853570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

10.otbn_ctrl_redun.113756548735731167439320650350169031657861339481451969984024727151605719488921
Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/10.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13406260 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13406260 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  13406260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.63465729328458683675683694983471480295145341839806998857932814120754712753728
    Line 526, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7660612776 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7660612776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.otbn_stress_all_with_rand_reset.32920998846157738804989095318293618163266810779003984370011786856891951313306
    Line 152, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2596005918 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2596005918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
- Test otbn_passthru_mem_tl_intg_err has 2 failures.
  - 6.otbn_passthru_mem_tl_intg_err.60227542111987583326834794939047039458066007051661797710029659312906198834156
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   4010849 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   4010849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 16.otbn_passthru_mem_tl_intg_err.114352240098678138606515979197388301676176959033325930814317609077643383701937
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/16.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   2799186 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   2799186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.72843746894929921791114253287877145906922227798929909594997949657233787079647
    Line 362, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1223026734 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1223026734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 2.otbn_passthru_mem_tl_intg_err.100571424515729371750308366300175063920391855114413979235001146907902658599326
    Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 110258505 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 110258505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```