46e7cd6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 10.000s | 298.079us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 4.000s | 27.895us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 4.000s | 12.632us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 386.890us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 240.737us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 115.020us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 4.000s | 12.632us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 240.737us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 57.117m | 600.000ms | 27 | 50 | 54.00 |
| V2 | cnt_rollover | cnt_rollover | 1.000m | 2.520ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 61.942us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.574h | 10.000s | 24 | 50 | 48.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 14.862us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 4.000s | 48.606us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 333.371us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 333.371us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 4.000s | 27.895us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 12.632us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 240.737us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 35.151us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 4.000s | 27.895us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 12.632us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 240.737us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 35.151us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 291 | 340 | 85.59 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 5.000s | 73.559us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 4.000s | 73.064us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 5.000s | 73.559us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.933m | 30.235ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.667m | 10.018ms | 38 | 50 | 76.00 | |
| TOTAL | 459 | 570 | 80.53 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.88 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 90.73 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
0.pattgen_stress_all_with_rand_reset.1954572341318820942221848164557834439085498425734463508056217952302636502647
Line 411, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6277421944 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 6277436322 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6277436322 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 8/10
UVM_INFO @ 6277602990 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.34962487328897124720582701714421365905267832856287254492154739326459435930481
Line 111, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 244840788 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 244847509 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 244847509 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 244887509 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 47 more failures.
Job timed out after * minutes has 18 failures:
2.pattgen_perf.66832532028866234850323389474179119808302767335961964263173117805061705080472
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
7.pattgen_perf.24232712450772918078546452264444963397471920373467792845114209666025493840950
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 10 more failures.
22.pattgen_stress_all.5551334173805293862779178008089815287343270622511220045041008202368755478801
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/22.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
26.pattgen_stress_all.65545831456589299466534828726217811650807383710160684674875250630447005196470
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 4 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 16 failures:
4.pattgen_stress_all.58323828971899366231188271123508644992313357393721487562243402056087331958555
Line 122, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 47795737 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10367
5.pattgen_stress_all.65884425437489741148439337186918151606144047549566352924322700156148029603706
Line 142, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
UVM_ERROR @ 22414766748 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @28621
... and 14 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 14 failures:
0.pattgen_perf.60105860459857433470848994286551295833994472814785028770765721931149688646893
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pattgen_perf.25451222501540522546289523557449978049362379323645489740004309678916284582535
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
1.pattgen_stress_all.31106885827147904419604774111062862316633357350313891807310299643290465831910
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pattgen_stress_all.94510416627134986836481154615400688177639745218622564045977790854520570386900
Line 135, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
5.pattgen_inactive_level.72708098244697400089881986996096441158406146211322114073842395744412197717284
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10019106440 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3ea02850, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10019106440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.pattgen_inactive_level.16783928709097855691800363572027050573286761105452445827012042119485576701969
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10288505737 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcedb6b90, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10288505737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
8.pattgen_inactive_level.2297711751606558310294866989153744520635915196889805198928028408005309756343
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009200227 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x751fe10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10009200227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.pattgen_inactive_level.91099894608905061751781798632648257385012319460217388802306098388158731454194
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002715976 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xefd8c1d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002715976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 2 failures:
Test pattgen_stress_all has 1 failures.
25.pattgen_stress_all.29159051231962606434201160744542824348016661705754045009000410506159894580011
Line 115, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log
UVM_ERROR @ 158530493 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
Test pattgen_stress_all_with_rand_reset has 1 failures.
45.pattgen_stress_all_with_rand_reset.78932579523405941630092486967176764628141612306708217273722927620362708832157
Line 117, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 347789328 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
4.pattgen_inactive_level.20342841303789687574632247176992652599318569590077761614586510712834727173489
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021250365 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe7e9b8d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10021250365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
15.pattgen_inactive_level.58887486064110165800450296428060308431268175628224295231148867769395601955885
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10018412526 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa6c3e390, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10018412526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
31.pattgen_inactive_level.13016815106516289883181991351411359645261355982447783550860061167799535994379
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008010771 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe50ce550, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10008010771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
35.pattgen_inactive_level.1972601166950951468338299762482824993718190408057126403448787819822106763869
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10055935185 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3fcae1d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10055935185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
36.pattgen_inactive_level.75215086949586798263809251051429621516629031029950181978716546440650309241371
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025372404 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x94e1fb90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10025372404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
38.pattgen_inactive_level.47634676074847928191942587786575177755277752031234603127630767696528176319450
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10205670466 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x51ec8210, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10205670466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
39.pattgen_inactive_level.75857096265678839843905374133872903278400928671570093258802611029747135848724
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025955787 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbea99410, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10025955787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
49.pattgen_inactive_level.77569903591142680349411629866271757174047014169593302880585201472274462221327
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002731388 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa7bca950, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
UVM_INFO @ 10002731388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---