ROM_CTRL/32KB Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.770s	181.493us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.150s	309.852us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.500s	2.092ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.430s	172.217us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.560s	555.864us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.700s	626.295us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.500s	2.092ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.560s	555.864us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.700s	578.864us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.110s	166.651us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.510s	263.842us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	29.970s	604.430us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.260s	225.089us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.720s	1.270ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.740s	180.225us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.740s	180.225us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.150s	309.852us	5	5	100.00
		rom_ctrl_csr_rw	9.500s	2.092ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.560s	555.864us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.820s	535.793us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.150s	309.852us	5	5	100.00
		rom_ctrl_csr_rw	9.500s	2.092ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.560s	555.864us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.820s	535.793us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	34.180s	11.181ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.930m	2.925ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.321m	559.694us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.930m	2.925ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.930m	2.925ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.930m	2.925ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.930m	2.925ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.770s	181.493us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.770s	181.493us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.770s	181.493us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.321m	559.694us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
		rom_ctrl_kmac_err_chk	11.260s	225.089us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	55.580s	2.558ms	1	20	5.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	34.180s	11.181ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.930m	2.925ms	5	5	100.00
V2S		TOTAL			46	65	70.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	14.005m	14.281ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			247	266	92.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.60	100.00	98.83	100.00	93.33	100.00	98.97	99.05

Failure Buckets

• Job timed out after * minutes has 16 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 16 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.102898864474708010640580335582988789188342226468187656934710775712902252534835
      Log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        Job timed out after 60 minutes
      

    • 1.rom_ctrl_corrupt_sig_fatal_chk.62238030335755471192512606581809200654073872288085332351188604876300798118527
      Log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 14 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.5235543315836282158921225122694914247312623302186609255558275225539880172401
      Line 91, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 829973689 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 829973689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.rom_ctrl_corrupt_sig_fatal_chk.89819533336997545967841469685117076808290774218809710480952511863192637623602
      Line 82, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1199118315 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1199118315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(counter_lnt -> kmac_rom_vld_o)' has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 16.rom_ctrl_corrupt_sig_fatal_chk.16178236424552332699487391507611463696276200146606228773162982673377544401812
      Line 86, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

            Offending '(counter_lnt -> kmac_rom_vld_o)'
        UVM_ERROR @ 1400129392 ps: (rom_ctrl_fsm.sv:317) [ASSERT FAILED] CounterLntImpliesKmacRomVldO_A
        UVM_INFO @ 1400129392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---