RV_TIMER Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.290s	39.892us	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.920s	14.780us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.290s	37.153us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.190s	636.985us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.350s	45.000us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.550s	96.291us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.290s	37.153us	20	20	100.00
		rv_timer_csr_aliasing	2.350s	45.000us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	19.800s	29.285ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.523m	199.504ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	20.837m	1.682s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	20.837m	1.682s	50	50	100.00
V2	stress	rv_timer_stress_all	11.211m	522.019ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.290s	24.143us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	5.130s	653.631us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	5.130s	653.631us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.920s	14.780us	5	5	100.00
		rv_timer_csr_rw	2.290s	37.153us	20	20	100.00
		rv_timer_csr_aliasing	2.350s	45.000us	5	5	100.00
		rv_timer_same_csr_outstanding	2.530s	78.344us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.920s	14.780us	5	5	100.00
		rv_timer_csr_rw	2.290s	37.153us	20	20	100.00
		rv_timer_csr_aliasing	2.350s	45.000us	5	5	100.00
		rv_timer_same_csr_outstanding	2.530s	78.344us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	2.260s	102.897us	5	5	100.00
		rv_timer_tl_intg_err	3.130s	1.270ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.130s	1.270ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.515m	26.907ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			619	620	99.84

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.14	99.65	99.08	92.06	--	99.13	99.68	63.25

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test rv_timer_disabled has 1 failures.

    • 49.rv_timer_disabled.19175353862827519218358214315431574615863856621021038057150367697393420341135
      Line 73, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/49.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---