SPI_DEVICE/1R1W Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.962m	523.956ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	3.030s	170.942us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.400s	97.045us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.430s	1.877ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.800s	612.632us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.170s	592.419us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.400s	97.045us	20	20	100.00
		spi_device_csr_aliasing	19.800s	612.632us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.260s	59.603us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.500s	29.466us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.470s	27.454us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.320s	1.885us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.130s	2.636us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.780s	273.770us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.780s	273.770us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.980s	9.702ms	50	50	100.00
		spi_device_tpm_sts_read	2.650s	93.954us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.460s	17.970ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.710s	37.986ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.480s	13.453ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.480s	13.453ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.950s	4.046ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.950s	4.046ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.950s	4.046ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.950s	4.046ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.950s	4.046ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.140s	57.203ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.431m	11.969ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.431m	11.969ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.431m	11.969ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	47.020s	4.132ms	50	50	100.00
		spi_device_read_buffer_direct	21.800s	2.421ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.431m	11.969ms	50	50	100.00
		spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.231m	262.241ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.820s	1.817ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	22.820s	1.817ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.962m	523.956ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.638m	333.290ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.386m	163.367ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.380s	87.675us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.410s	41.882us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.380s	529.489us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.380s	529.489us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	3.030s	170.942us	5	5	100.00
		spi_device_csr_rw	4.400s	97.045us	20	20	100.00
		spi_device_csr_aliasing	19.800s	612.632us	5	5	100.00
		spi_device_same_csr_outstanding	6.120s	197.588us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	3.030s	170.942us	5	5	100.00
		spi_device_csr_rw	4.400s	97.045us	20	20	100.00
		spi_device_csr_aliasing	19.800s	612.632us	5	5	100.00
		spi_device_same_csr_outstanding	6.120s	197.588us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	2.550s	154.009us	5	5	100.00
		spi_device_tl_intg_err	25.090s	2.190ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.090s	2.190ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.688m	73.621ms	49	50	98.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.22	83.25	89.36	98.37	95.66	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.39605479778479562614305939310063682445829222522187187833001754209464412301045
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1731992 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[39])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1731992 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1731992 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[935])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.84969045484078203483999673090472261336413679656471976957379216146721444662683
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    873978 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[12])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    873978 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    873978 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[908])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.107540195672434701751782797647975656207278574439302512103323821710669948402553
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   1854957 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1854957 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
  UVM_ERROR @   1871957 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x839648 [100000111001011001001000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
  UVM_ERROR @   1871957 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x839648 [100000111001011001001000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])

UVM_ERROR (spi_device_scoreboard.sv:2235) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

39.spi_device_cfg_cmd.2587614933421891420560701162674603632151320970618842615154334944920151825064
Line 80, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 4093978261 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc34f82) != exp '{'{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h390e77, wel:'h0, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 4094999078 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc34f82) != exp '{'{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h1705e4, wel:'h0, busy:'h0}}
  UVM_ERROR @ 4095207408 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc34f82) != exp '{'{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h1705e4, wel:'h0, busy:'h0}}
  UVM_ERROR @ 4095519903 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc34f82) != exp '{'{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h1705e4, wel:'h0, busy:'h0}}
  UVM_ERROR @ 4095686567 ps: (spi_device_scoreboard.sv:2235) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc34f82) != exp '{'{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h132a71, wel:'h1, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h30d3e0, wel:'h0, busy:'h0}, '{other_status:'h1705e4, wel:'h0, busy:'h0}}

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 49.spi_device_flash_mode_ignore_cmds.29100152934458762160680512762368017479877751223130728330902647515485842916455
    Log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```