SPI_DEVICE/2P Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.764m	224.688ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	3.050s	41.519us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.300s	374.817us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.910s	2.089ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.900s	320.395us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.230s	122.521us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.300s	374.817us	20	20	100.00
		spi_device_csr_aliasing	20.900s	320.395us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.360s	13.682us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	4.000s	717.827us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.500s	59.367us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.810s	114.504us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	2.440s	1.588us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.720s	1.094ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.720s	1.094ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.950s	23.412ms	50	50	100.00
		spi_device_tpm_sts_read	2.890s	140.357us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.300s	12.276ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	53.240s	148.560ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.560s	26.636ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.560s	26.636ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.420s	6.155ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.420s	6.155ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.420s	6.155ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.420s	6.155ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.420s	6.155ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	49.280s	187.902ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.527m	18.254ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.527m	18.254ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.527m	18.254ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.940s	5.380ms	50	50	100.00
		spi_device_read_buffer_direct	20.630s	2.775ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.527m	18.254ms	50	50	100.00
		spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.117m	165.897ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.000s	4.504ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.000s	4.504ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.764m	224.688ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.724m	37.230ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.352m	208.349ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.420s	20.966us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.490s	80.502us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.070s	1.820ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.070s	1.820ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	3.050s	41.519us	5	5	100.00
		spi_device_csr_rw	4.300s	374.817us	20	20	100.00
		spi_device_csr_aliasing	20.900s	320.395us	5	5	100.00
		spi_device_same_csr_outstanding	5.900s	160.587us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	3.050s	41.519us	5	5	100.00
		spi_device_csr_rw	4.300s	374.817us	20	20	100.00
		spi_device_csr_aliasing	20.900s	320.395us	5	5	100.00
		spi_device_same_csr_outstanding	5.900s	160.587us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	2.980s	93.801us	5	5	100.00
		spi_device_tl_intg_err	22.840s	821.328us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.840s	821.328us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.438m	478.627ms	50	50	100.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.47	99.02	96.31	83.25	89.36	98.46	95.65	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.86833864984206081408195669447895872778703117442993725671513066725805806519632
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    868737 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    868737 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    900737 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x642fc1 [11001000010111111000001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    900737 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)