SPI_HOST Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	5.483m	32.477ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	17.551us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	31.129us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	404.251us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	48.101us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	53.729us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	31.129us	20	20	100.00
		spi_host_csr_aliasing	5.000s	48.101us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	117.750us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	88.407us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	43.000s	108.166us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	48.000s	174.504us	50	50	100.00
		spi_host_error_cmd	42.000s	31.860us	50	50	100.00
		spi_host_event	6.750m	27.822ms	50	50	100.00
V2	clock_rate	spi_host_speed	47.000s	481.797us	50	50	100.00
V2	speed	spi_host_speed	47.000s	481.797us	50	50	100.00
V2	chip_select_timing	spi_host_speed	47.000s	481.797us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.250m	5.742ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	43.000s	176.360us	50	50	100.00
V2	cpol_cpha	spi_host_speed	47.000s	481.797us	50	50	100.00
V2	full_cycle	spi_host_speed	47.000s	481.797us	50	50	100.00
V2	duplex	spi_host_smoke	5.483m	32.477ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	5.483m	32.477ms	50	50	100.00
V2	stress_all	spi_host_stress_all	5.000m	15.058ms	49	50	98.00
V2	spien	spi_host_spien	3.350m	9.487ms	50	50	100.00
V2	stall	spi_host_status_stall	5.483m	10.591ms	44	50	88.00
V2	Idlecsbactive	spi_host_idlecsbactive	44.000s	472.809us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	48.000s	174.504us	50	50	100.00
V2	alert_test	spi_host_alert_test	42.000s	37.008us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	105.165us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	287.497us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	287.497us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	17.551us	5	5	100.00
		spi_host_csr_rw	5.000s	31.129us	20	20	100.00
		spi_host_csr_aliasing	5.000s	48.101us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	67.855us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	17.551us	5	5	100.00
		spi_host_csr_rw	5.000s	31.129us	20	20	100.00
		spi_host_csr_aliasing	5.000s	48.101us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	67.855us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	233.332us	20	20	100.00
		spi_host_sec_cm	42.000s	155.023us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	233.332us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	56.217m	79.271ms	5	10	50.00
		TOTAL			828	840	98.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.27	96.74	93.21	98.69	94.51	88.02	100.00	96.86	91.56

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
- Test spi_host_upper_range_clkdiv has 2 failures.
  - 1.spi_host_upper_range_clkdiv.44087869316140761127372945747727548798701931794830837800410994150412026712702
    Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002853086 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe056e614, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100002853086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.spi_host_upper_range_clkdiv.86957097121671707578717337976837284514105969320568949097896562250455296526719
    Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100003749110 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa63e1f94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100003749110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 2.spi_host_upper_range_clkdiv.19041354290498053274255671997903522594738203482017959080649822527005220511480
    Line 204, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 6.spi_host_upper_range_clkdiv.72050958236060544197452443224365534621074258606714984121596768396166607203483
    Line 142, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002378767 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9c029c54, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 100002378767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 8.spi_host_upper_range_clkdiv.5608667535694556665997639964415440692849184609304216264443964806657185589181
    Log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=78) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 10.spi_host_status_stall.22515657728019336824037104092510576598924229069466617491481759532897097229507
    Line 670, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 19327326911 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x44f36754, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
  UVM_INFO @ 19327326911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=77) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 14.spi_host_status_stall.96131977104240038984570139765247072248958747403480953423297567622334318876666
    Line 693, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10590529098 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1e98b9d4, Comparison=CompareOpEq, exp_data=0x1, call_count=77)
  UVM_INFO @ 10590529098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=80) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 18.spi_host_status_stall.80297435310133894614605004401204523090930134506820338334675549041675949685524
    Line 684, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10039393957 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa4238894, Comparison=CompareOpEq, exp_data=0x1, call_count=80)
  UVM_INFO @ 10039393957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36) has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 27.spi_host_stress_all.957947180362635584323524175147778431244421686708323055990602829502300535531
    Line 283, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/27.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 15057901406 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x55f0cb94, Comparison=CompareOpEq, exp_data=0x0, call_count=36)
  UVM_INFO @ 15057901406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

32.spi_host_status_stall.32738869877553031380927106263837646616942647574568871695331405493075994925346
Line 729, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/32.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 9228022861 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 9228022861 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=9228023000 ps
  UVM_INFO @ 9228022861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=88) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 42.spi_host_status_stall.39642506603353744927484448926528577590699497808972696398972036342740995149222
    Line 757, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 12045575429 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbdf2c994, Comparison=CompareOpEq, exp_data=0x1, call_count=88)
  UVM_INFO @ 12045575429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=87) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 45.spi_host_status_stall.109860910445342014723159809508415457595176646868933329700763477847668048987865
    Line 732, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10294857819 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1e86e54, Comparison=CompareOpEq, exp_data=0x1, call_count=87)
  UVM_INFO @ 10294857819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```