SRAM_CTRL/MAIN Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.798m	1.618ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.170s	62.842us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.280s	96.656us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.750s	181.160us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.070s	80.916us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.050s	3.212ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.280s	96.656us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	80.916us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.065m	89.844ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.059m	10.727ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.828m	26.862ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.043m	28.518ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.602m	638.687ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.975m	19.545ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.848m	12.267ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.972m	11.409ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.778m	9.260ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.600m	115.636ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.831m	2.829ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.692m	3.735ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.984m	2.176ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.228m	20.807ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.710s	3.068ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.674h	289.737ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	24.516us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.280s	800.768us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.280s	800.768us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.170s	62.842us	5	5	100.00
		sram_ctrl_csr_rw	2.280s	96.656us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	80.916us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.290s	154.304us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.170s	62.842us	5	5	100.00
		sram_ctrl_csr_rw	2.280s	96.656us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	80.916us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.290s	154.304us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.042m	7.513ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.310s	30.678us	0	5	0.00
		sram_ctrl_tl_intg_err	4.510s	418.521us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.310s	30.678us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.510s	418.521us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.228m	20.807ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.228m	20.807ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.280s	96.656us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.972m	11.409ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.972m	11.409ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.972m	11.409ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.848m	12.267ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.310s	5.125ms	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.042m	7.513ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.260s	4.707ms	37	50	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.798m	1.618ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.798m	1.618ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.972m	11.409ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.310s	30.678us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.848m	12.267ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.310s	30.678us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.310s	30.678us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.798m	1.618ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.310s	30.678us	0	5	0.00
V2S		TOTAL			117	145	80.69
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.422m	2.442ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1162	1190	97.65

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	99.29	93.01	85.18	100.00	98.07	98.59	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 13 failures:
  • Test sram_ctrl_readback_err has 13 failures.

    • 6.sram_ctrl_readback_err.97733439917962537666481902761659046247116973954177917623554844521069535374476
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 682609637 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1e) != exp (0x78)
        UVM_INFO @ 682609637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_readback_err.53502703035749787527847616007894457163806298549540387169643513114917583640349
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2761132040 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x23) != exp (0x6c)
        UVM_INFO @ 2761132040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• Offending 'reqfifo_rvalid' has 10 failures:
  • Test sram_ctrl_mubi_enc_err has 10 failures.

    • 3.sram_ctrl_mubi_enc_err.109853815297138588547828186215573942192134100412392564852837231202121987666165
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1067723323 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1067723323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_mubi_enc_err.3407175731872292230383787929706050368841253335050505792983300842766549598124
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 715065952 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 715065952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending '(!$isunknown(rdata_o))' has 3 failures:
  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.72116097674790722471640317102247221778971024448586167821925863776656465324983
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  14292875 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  14292875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.41481409468306491929735930703399831802223333957305410717145387410346113192462
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2830545 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2830545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:
  • Test sram_ctrl_sec_cm has 2 failures.

    • 2.sram_ctrl_sec_cm.103080162893898327491388811435753901923616299786235141062297625713626394109350
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  30677518 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  30677518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.51108804199359663829919559587230778563714283238629925220691735303480719796561
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7844364 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7844364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---