SRAM_CTRL/RET Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: 46e7cd6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.767m	138.065us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.050s	16.980us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.190s	15.245us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.440s	125.771us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.190s	58.627us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.930s	153.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.190s	15.245us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	58.627us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	18.660s	11.307ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.660s	775.874us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.997m	113.328ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.432m	39.016ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.515m	10.598ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.256m	19.930ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.680s	898.900us	50	50	100.00
V2	executable	sram_ctrl_executable	21.613m	56.426ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.366m	774.074us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.235m	484.823ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.750m	277.756us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.467m	152.383us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.641m	583.603us	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.860m	70.767ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.660s	136.917us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.026h	29.066ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.180s	39.239us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.760s	520.988us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.760s	520.988us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.050s	16.980us	5	5	100.00
		sram_ctrl_csr_rw	2.190s	15.245us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	58.627us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.280s	34.383us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.050s	16.980us	5	5	100.00
		sram_ctrl_csr_rw	2.190s	15.245us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	58.627us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.280s	34.383us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.230s	493.624us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.260s	20.697us	0	5	0.00
		sram_ctrl_tl_intg_err	4.110s	854.965us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.260s	20.697us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.110s	854.965us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.860m	70.767ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.860m	70.767ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.190s	15.245us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.613m	56.426ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.613m	56.426ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.613m	56.426ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.680s	898.900us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.700s	131.669us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.230s	493.624us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.760s	488.194us	41	50	82.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.767m	138.065us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.767m	138.065us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.613m	56.426ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.260s	20.697us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.680s	898.900us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.260s	20.697us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.260s	20.697us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.767m	138.065us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.260s	20.697us	0	5	0.00
V2S		TOTAL			126	145	86.90
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.007m	7.594ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1171	1190	98.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	98.03	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 9 failures:

  • Test sram_ctrl_readback_err has 9 failures.

    • 9.sram_ctrl_readback_err.60596133941880168121428367276609826926950377041400651392682232767372529061057
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 126351636 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5b) != exp (0x34)
        UVM_INFO @ 126351636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.sram_ctrl_readback_err.99923809170836933993396656519981997097914514758079182143135321804251847370801
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  59052520 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x52) != exp (0x40)
        UVM_INFO @  59052520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 4.sram_ctrl_mubi_enc_err.107159799063568182791951416963792830829228680326288660609854972260469842228715
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 117507479 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 117507479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_mubi_enc_err.32605772526543966560335681428372935791376702474815766654409736446217186713696
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  92136422 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  92136422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.16808030029636478653360549348865757595315369659255955383935960672919494590191
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3276254 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3276254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.24051528612520774183838515059478635865007016922559212947783585369902548347768
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6641904 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6641904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.34716143200158958284210408370870695889264734786745843352096963676907760131823
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3996446 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3996446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.20915475456415130272176839395818552603094774248029697540003183984303949126062
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   2165105 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   2165105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---