SYSRST_CTRL Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	10.100s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	12.000s	2.447ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	9.550s	2.209ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	9.340s	2.513ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	24.990s	6.028ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	9.580s	2.062ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	6.166m	75.485ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	12.820s	3.005ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	9.570s	2.042ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	9.580s	2.062ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.820s	3.005ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.242m	172.835ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.866m	184.623ms	99	100	99.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.801m	267.357ms	49	50	98.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	9.891m	1.674s	48	50	96.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	12.270s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	9.600s	2.153ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	9.186m	772.402ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	12.180s	2.616ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	11.298m	2.054s	45	50	90.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	36.160s	41.373ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	7.962m	213.800ms	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	9.780s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	9.960s	2.010ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	11.580s	2.059ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	11.580s	2.059ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	24.990s	6.028ms	5	5	100.00
		sysrst_ctrl_csr_rw	9.580s	2.062ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.820s	3.005ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	27.950s	7.527ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	24.990s	6.028ms	5	5	100.00
		sysrst_ctrl_csr_rw	9.580s	2.062ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.820s	3.005ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	27.950s	7.527ms	20	20	100.00
V2		TOTAL			681	692	98.41
V2S	tl_intg_err	sysrst_ctrl_sec_cm	47.350s	42.038ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.818m	42.435ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.818m	42.435ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	23.980s	6.267ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			920	932	98.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.90	99.24	97.96	100.00	95.51	99.44	99.33	93.79

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 5 failures:

Test sysrst_ctrl_ultra_low_pwr has 2 failures.

6.sysrst_ctrl_ultra_low_pwr.2484677886950083214514996727142124873406370366413375570552284291297513955961
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5626040117 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 5626070116 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 5626070116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sysrst_ctrl_ultra_low_pwr.32644019489894121134925289900295616038409437283341243105298622704497780730720
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 4446394631 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 4446727963 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 4446727963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_edge_detect has 2 failures.

14.sysrst_ctrl_edge_detect.15202444781020869962684001926965504054798965934319283047858650311463901907037
Line 385, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 2433558420 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 2433588722 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 2433588722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.sysrst_ctrl_edge_detect.83715549780479619515682847101306436990367860564506067864334290112729247093021
Line 387, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 2826072863 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 2826104440 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 2826104440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all has 1 failures.

31.sysrst_ctrl_stress_all.43973844701775156753843013270174533227803992150212838761341643878286194036579
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 5656018599 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 5656042524 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 5656042524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 3 failures:

Test sysrst_ctrl_ultra_low_pwr has 3 failures.

38.sysrst_ctrl_ultra_low_pwr.44370306114623030884095536317101041390923537091022527897954142769758917445326
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2220172618 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 956602672618 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 956602672618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.sysrst_ctrl_ultra_low_pwr.98190924922520026175622217115697635515932618306269230563212751431354332887249
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2130036156 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 2477536156 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2477536156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 3.sysrst_ctrl_stress_all.86314945672184982096158901971762456227565108674701848891929484395701274660601
    Line 386, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 11940906190 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 11940906190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_auto_blk_key_output has 1 failures.

12.sysrst_ctrl_auto_blk_key_output.50868573274131970129695603418288227278521363154765905973252225372094348376590
Line 381, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest/run.log

  UVM_ERROR @ 2286088532 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2401263148 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 28
  UVM_INFO @ 2711088532 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:47
  UVM_INFO @ 2811260688 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 2d
  UVM_INFO @ 3126088532 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:51

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

36.sysrst_ctrl_combo_detect_with_pre_cond.49121142591651588245881396751026510110734516875540401507787015277500757944188
Line 498, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 110905876288 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 111015876288 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
  UVM_INFO @ 111015876288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

44.sysrst_ctrl_stress_all_with_rand_reset.105637149650490072525284126643580890516562705473456736871489169572878297307811
Line 398, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5153084859 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 5153084859 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5153084859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---