UART Simulation Results

Sunday April 27 2025 00:14:02 UTC

GitHub Revision: `46e7cd6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.012m	11.092ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.220s	50.942us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.280s	25.016us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.480s	59.663us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.490s	29.012us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.920s	57.984us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.280s	25.016us	20	20	100.00
		uart_csr_aliasing	2.490s	29.012us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.014m	137.682ms	50	50	100.00
V2	parity	uart_smoke	1.012m	11.092ms	50	50	100.00
		uart_tx_rx	4.014m	137.682ms	50	50	100.00
V2	parity_error	uart_intr	7.733m	335.957ms	50	50	100.00
		uart_rx_parity_err	7.600m	159.975ms	50	50	100.00
V2	watermark	uart_tx_rx	4.014m	137.682ms	50	50	100.00
		uart_intr	7.733m	335.957ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.831m	234.162ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.485m	115.722ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.121m	226.169ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.733m	335.957ms	50	50	100.00
V2	rx_break_err	uart_intr	7.733m	335.957ms	50	50	100.00
V2	rx_timeout	uart_intr	7.733m	335.957ms	50	50	100.00
V2	perf	uart_perf	21.091m	27.471ms	50	50	100.00
V2	sys_loopback	uart_loopback	29.890s	12.080ms	50	50	100.00
V2	line_loopback	uart_loopback	29.890s	12.080ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.151m	215.093ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.496m	48.064ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	49.090s	6.625ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.243m	7.101ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.808m	132.313ms	50	50	100.00
V2	stress_all	uart_stress_all	19.134m	265.772ms	50	50	100.00
V2	alert_test	uart_alert_test	2.210s	13.270us	50	50	100.00
V2	intr_test	uart_intr_test	2.290s	15.846us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.770s	550.788us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.770s	550.788us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.220s	50.942us	5	5	100.00
		uart_csr_rw	2.280s	25.016us	20	20	100.00
		uart_csr_aliasing	2.490s	29.012us	5	5	100.00
		uart_same_csr_outstanding	2.420s	32.983us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.220s	50.942us	5	5	100.00
		uart_csr_rw	2.280s	25.016us	20	20	100.00
		uart_csr_aliasing	2.490s	29.012us	5	5	100.00
		uart_same_csr_outstanding	2.420s	32.983us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	2.600s	249.301us	5	5	100.00
		uart_tl_intg_err	3.010s	79.816us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.010s	79.816us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.908m	4.640ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.17	98.25	91.55	--	98.15	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

9.uart_stress_all_with_rand_reset.32592684927946077753156285209762405783740477043372087147370711583887817800492
Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   4739869 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
  UVM_INFO @ 222912002 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 223120332 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 15.uart_noise_filter.48380029485739483435328191618634695552403761636262807361030181339083210029726
    Line 84, in log /nightly/runs/scratch/master/uart-sim-vcs/15.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

38.uart_stress_all_with_rand_reset.41237533854057389193304789676739427404545315071426155331122710344197935706983
Line 136, in log /nightly/runs/scratch/master/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6062994440 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6062994440 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 6063145955 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 4/5

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

Test uart_fifo_reset has 1 failures.

281.uart_fifo_reset.53734845916922624196029621034688028728771836508722381923003859217020101415431
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/281.uart_fifo_reset/latest/run.log

  UVM_ERROR @   2116747 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 458803159 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10
  UVM_INFO @ 55827914329 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10
  UVM_INFO @ 56650082838 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
  UVM_INFO @ 64241365639 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10