ADC_CTRL Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	24.140s	5.795ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.330s	762.703us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.860s	520.179us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.129m	53.143ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	7.060s	1.458ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.050s	497.936us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.860s	520.179us	20	20	100.00
		adc_ctrl_csr_aliasing	7.060s	1.458ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.844m	493.796ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.586m	490.050ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	17.775m	489.749ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	21.938m	489.720ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.294m	634.088ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	18.963m	589.681ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.136m	557.770ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	21.459m	530.680ms	33	50	66.00
V2	poweron_counter	adc_ctrl_poweron_counter	21.190s	5.536ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.325m	43.692ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.963m	139.887ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	24.584m	759.542ms	49	50	98.00
V2	alert_test	adc_ctrl_alert_test	3.810s	500.602us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.900s	533.899us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.180s	736.147us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.180s	736.147us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.330s	762.703us	5	5	100.00
		adc_ctrl_csr_rw	3.860s	520.179us	20	20	100.00
		adc_ctrl_csr_aliasing	7.060s	1.458ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.950s	4.353ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.330s	762.703us	5	5	100.00
		adc_ctrl_csr_rw	3.860s	520.179us	20	20	100.00
		adc_ctrl_csr_aliasing	7.060s	1.458ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.950s	4.353ms	20	20	100.00
V2		TOTAL			718	740	97.03
V2S	tl_intg_err	adc_ctrl_sec_cm	15.090s	4.646ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.980s	8.375ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.980s	8.375ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.135m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			896	920	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.11	96.45	100.00	100.00	99.01	98.06	91.06

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
- Test adc_ctrl_clock_gating has 7 failures.
  - 7.adc_ctrl_clock_gating.89756343095573061560167668213414723573489178655978531481762267097211102404422
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.adc_ctrl_clock_gating.19740642368721069634587816930695448168948688661263590145328183040207586756286
    Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
- Test adc_ctrl_filters_both has 1 failures.
  - 13.adc_ctrl_filters_both.60360911755649987320428641192455665203794777984769422400478745091070783771336
    Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all has 1 failures.
  - 24.adc_ctrl_stress_all.60943070490556505167441027698313492945984933095297658358197526385402537763363
    Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.adc_ctrl_stress_all_with_rand_reset.46626866365744976495500253551256842536082763128401126664763222110259302357458
    Line 173, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 9 failures:
- Test adc_ctrl_clock_gating has 8 failures.
  - 1.adc_ctrl_clock_gating.39631075421778059714623672157379418918379665173864034831845318165764644759344
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 24703086162 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 24703086162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.adc_ctrl_clock_gating.30085824212626212875745331097898739689135006560958878237085535892493175161657
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 16681083919 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 16681083919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.adc_ctrl_stress_all_with_rand_reset.110194174235560953058829169840401249467427366782317180230606734816397504323916
    Line 263, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70751464193 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 70751464193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:

Test adc_ctrl_filters_interrupt has 1 failures.

3.adc_ctrl_filters_interrupt.103211296237987728616872829684521436600755738017748265495014064470880307352722
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 252203874342 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 252203874342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 2 failures.

8.adc_ctrl_clock_gating.84835362477649140100397460317285736359893244998215438313449910358726352252279
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 82085982191 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82085982191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.adc_ctrl_clock_gating.1848547432269527075145791436282475361613873562670749432875710220148470163064
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 79152896077 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 79152896077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 2 failures.

26.adc_ctrl_filters_both.26490407720090793532212358376786364545601176373629568300204359170546122725467
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 164787186966 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 164787186966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.adc_ctrl_filters_both.112989066794127184908252534076595699130027844042020536515538639056119325667208
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 276688658469 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 276688658469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---