AES/MASKED Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	83.077us	1	1	100.00
V1	smoke	aes_smoke	7.000s	547.562us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	76.636us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	95.468us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.211ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	133.414us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	130.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	95.468us	20	20	100.00
		aes_csr_aliasing	6.000s	133.414us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	547.562us	50	50	100.00
		aes_config_error	9.000s	854.319us	50	50	100.00
		aes_stress	46.000s	2.559ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	547.562us	50	50	100.00
		aes_config_error	9.000s	854.319us	50	50	100.00
		aes_stress	46.000s	2.559ms	50	50	100.00
V2	back2back	aes_stress	46.000s	2.559ms	50	50	100.00
		aes_b2b	23.000s	434.466us	50	50	100.00
V2	backpressure	aes_stress	46.000s	2.559ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	547.562us	50	50	100.00
		aes_config_error	9.000s	854.319us	50	50	100.00
		aes_stress	46.000s	2.559ms	50	50	100.00
		aes_alert_reset	12.000s	741.920us	49	50	98.00
V2	failure_test	aes_man_cfg_err	7.000s	223.821us	50	50	100.00
		aes_config_error	9.000s	854.319us	50	50	100.00
		aes_alert_reset	12.000s	741.920us	49	50	98.00
V2	trigger_clear_test	aes_clear	11.000s	661.847us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	1.421ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	741.920us	49	50	98.00
V2	stress	aes_stress	46.000s	2.559ms	50	50	100.00
V2	sideload	aes_stress	46.000s	2.559ms	50	50	100.00
		aes_sideload	1.283m	4.433ms	50	50	100.00
V2	deinitialization	aes_deinit	24.000s	1.402ms	50	50	100.00
V2	stress_all	aes_stress_all	58.000s	1.204ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	57.126us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	89.802us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	89.802us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	76.636us	5	5	100.00
		aes_csr_rw	5.000s	95.468us	20	20	100.00
		aes_csr_aliasing	6.000s	133.414us	5	5	100.00
		aes_same_csr_outstanding	6.000s	387.621us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	76.636us	5	5	100.00
		aes_csr_rw	5.000s	95.468us	20	20	100.00
		aes_csr_aliasing	6.000s	133.414us	5	5	100.00
		aes_same_csr_outstanding	6.000s	387.621us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	13.000s	711.219us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	298.703us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	298.703us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	298.703us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	298.703us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	530.964us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.153ms	5	5	100.00
		aes_tl_intg_err	6.000s	193.643us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	193.643us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	741.920us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	298.703us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	547.562us	50	50	100.00
		aes_stress	46.000s	2.559ms	50	50	100.00
		aes_alert_reset	12.000s	741.920us	49	50	98.00
		aes_core_fi	25.000s	10.072ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	298.703us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	56.666us	50	50	100.00
		aes_stress	46.000s	2.559ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	46.000s	2.559ms	50	50	100.00
		aes_sideload	1.283m	4.433ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	56.666us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	56.666us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	56.666us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	56.666us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	56.666us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	46.000s	2.559ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	46.000s	2.559ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	771.780us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
		aes_ctr_fi	6.000s	53.886us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	771.780us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.004ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	771.780us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_ctr_fi	6.000s	53.886us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
		aes_ctr_fi	6.000s	53.886us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	741.920us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
		aes_ctr_fi	6.000s	53.886us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
		aes_ctr_fi	6.000s	53.886us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_ctr_fi	6.000s	53.886us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	771.780us	49	50	98.00
		aes_control_fi	41.000s	10.008ms	278	300	92.67
		aes_cipher_fi	44.000s	10.004ms	337	350	96.29
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	37.000s	2.981ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.59	96.43	99.41	95.68	97.99	97.78	98.96	98.79

Failure Buckets

Job timed out after * minutes has 14 failures:
- Test aes_control_fi has 14 failures.
  - 31.aes_control_fi.13267843602597741813204844879392688757794608209243762281149571240024400679463
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 33.aes_control_fi.57410774383707815976895887573156584599557264671240329078422675501221214665234
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 26.aes_cipher_fi.7985139107509834724907133959924309219848667580079784726558696192083437042976
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005477758 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005477758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 67.aes_cipher_fi.23924733573364550073655142311276922125863998206863380539223016871095701451496
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/67.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022903502 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022903502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 42.aes_control_fi.84523344874919719460418191195236252822835796951904302754124232822866761713996
    Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009360749 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009360749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 104.aes_control_fi.58056667995603004596658433740001825441456781220620979167490547411488948772743
    Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/104.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005836080 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005836080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.113087240815038815956873416948535356740239957325365391235854685610005640848810
Line 818, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2395188025 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2395188025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.14046142891672969421112318195674028131110554389724821204459660142012583254397
Line 348, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 133140609 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 133140609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.53530530652740135166516453356622662376525896542704435704525357350933487246739
    Line 534, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3014591235 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3014591235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.26779083548165697010015317730119833195321822057439470133478070213479445375005
    Line 156, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  55455769 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  55455769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 1 failures.

14.aes_alert_reset.51388704761563464156500346072938200921202372135026495644397302388226070899888
Line 4334, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/14.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 17081615 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 17065742 PS)
  UVM_ERROR @  17081615 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  17081615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

20.aes_fi.82575717174024689553190153543123394257899257598118575885175252730129657346578
Line 1947, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/20.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 10465841 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10445433 PS)
  UVM_ERROR @  10465841 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  10465841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 42.aes_core_fi.35038847272335284745430284937119828443009903653205321965466212171038242906926
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020387872 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020387872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 46.aes_core_fi.17623689007492795584672762900370018367004547062916988317640393526282750886820
    Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10072292159 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10072292159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.25882459381109908498427047278930663384903543673486589278802349078165681555759
    Line 1250, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2981110781 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2981110781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```