AES/UNMASKED Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	105.408us	1	1	100.00
V1	smoke	aes_smoke	6.000s	105.357us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	49.000s	83.259us	5	5	100.00
V1	csr_rw	aes_csr_rw	49.000s	64.221us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	51.000s	523.194us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	46.000s	102.575us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	44.000s	75.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	49.000s	64.221us	20	20	100.00
		aes_csr_aliasing	46.000s	102.575us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	105.357us	50	50	100.00
		aes_config_error	6.000s	870.045us	50	50	100.00
		aes_stress	7.000s	188.049us	50	50	100.00
V2	key_length	aes_smoke	6.000s	105.357us	50	50	100.00
		aes_config_error	6.000s	870.045us	50	50	100.00
		aes_stress	7.000s	188.049us	50	50	100.00
V2	back2back	aes_stress	7.000s	188.049us	50	50	100.00
		aes_b2b	9.000s	1.222ms	50	50	100.00
V2	backpressure	aes_stress	7.000s	188.049us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	105.357us	50	50	100.00
		aes_config_error	6.000s	870.045us	50	50	100.00
		aes_stress	7.000s	188.049us	50	50	100.00
		aes_alert_reset	6.000s	234.829us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	246.128us	50	50	100.00
		aes_config_error	6.000s	870.045us	50	50	100.00
		aes_alert_reset	6.000s	234.829us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	329.878us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	344.829us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	234.829us	50	50	100.00
V2	stress	aes_stress	7.000s	188.049us	50	50	100.00
V2	sideload	aes_stress	7.000s	188.049us	50	50	100.00
		aes_sideload	6.000s	441.298us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	132.892us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	1.731ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	116.960us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	50.000s	105.468us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	50.000s	105.468us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	49.000s	83.259us	5	5	100.00
		aes_csr_rw	49.000s	64.221us	20	20	100.00
		aes_csr_aliasing	46.000s	102.575us	5	5	100.00
		aes_same_csr_outstanding	46.000s	152.988us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	49.000s	83.259us	5	5	100.00
		aes_csr_rw	49.000s	64.221us	20	20	100.00
		aes_csr_aliasing	46.000s	102.575us	5	5	100.00
		aes_same_csr_outstanding	46.000s	152.988us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	370.258us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	49.000s	138.966us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	49.000s	138.966us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	49.000s	138.966us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	49.000s	138.966us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	50.000s	258.805us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	3.763ms	5	5	100.00
		aes_tl_intg_err	50.000s	448.370us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	50.000s	448.370us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	234.829us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	49.000s	138.966us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	105.357us	50	50	100.00
		aes_stress	7.000s	188.049us	50	50	100.00
		aes_alert_reset	6.000s	234.829us	50	50	100.00
		aes_core_fi	3.800m	10.009ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	49.000s	138.966us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	197.989us	50	50	100.00
		aes_stress	7.000s	188.049us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	188.049us	50	50	100.00
		aes_sideload	6.000s	441.298us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	197.989us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	197.989us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	197.989us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	197.989us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	197.989us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	188.049us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	188.049us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	213.135us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	150.727us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	213.135us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	29.000s	10.004ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	213.135us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_ctr_fi	6.000s	150.727us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	150.727us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	234.829us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	150.727us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	150.727us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_ctr_fi	6.000s	150.727us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	213.135us	49	50	98.00
		aes_control_fi	29.000s	10.016ms	282	300	94.00
		aes_cipher_fi	29.000s	10.004ms	332	350	94.86
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	18.000s	843.364us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.29	97.67	94.75	98.78	93.54	97.99	91.11	98.85	97.79

Failure Buckets

Job timed out after * minutes has 17 failures:
- Test aes_control_fi has 8 failures.
  - 7.aes_control_fi.3748726905287143283078073945987923931053764863806807273136749945512412808
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 32.aes_control_fi.2061823063024964772745025054302044757449994148945174178496259202043972136914
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 9 failures.
  - 72.aes_cipher_fi.51268441226008257887938760584204986344201388642386505305177219491272779480230
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 73.aes_cipher_fi.60921045399478897892061608589734552431539859057018892829578300030806552889451
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 8.aes_control_fi.52080931804968122827102263359293861204592297287895376119950194368071830184039
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008601236 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008601236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.aes_control_fi.6768976397513135713418885036035664503640308968831000289474291150875714950150
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010413874 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010413874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 5.aes_cipher_fi.17288370374299079242818161989398813844434620090121986088715236357361437085734
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012264444 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012264444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.aes_cipher_fi.68592790150821539735133239766360315086004089351542928900916596753738950125133
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10049584465 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10049584465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.34681217648046221352855977000522956926885365799190962657276493911794300545707
Line 1344, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 859562030 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 859562030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.85850573661171279750300863666988171221853661995575368578428134147098265814709
Line 1040, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 608473567 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 608473567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.97671606931775388034708611501598187464516811705365503579519098083356417281864
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  21129430 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  21129430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.95494685953112655810063325728046172130457551973091155942050310111541356130616
    Line 153, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  46773932 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  46773932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 8.aes_core_fi.87777578917004709108068455006543458106798984801623114122352895110110911057527
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004778042 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004778042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.aes_core_fi.82154919399591541138208975554511287878564204149309843704911389043121613932001
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002342734 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002342734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.18307869338263919793841143876787979260695197990978435407977239017930429063911
    Line 613, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1521656326 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1521656326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.67319229629726282078891078793832533048942953838747858367303309504423623138837
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  45871641 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  45871641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 29.aes_fi.45835683628644896742980357609076481722228595455354048628272521874000695083708
    Line 5541, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/29.aes_fi/latest/run.log
```
  UVM_FATAL @  58112572 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  58112572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 38.aes_core_fi.41668832385021822848944071742203023009409241510856046780049401274409655627705
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10031734493 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031734493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 52.aes_core_fi.75999403248070483633610786001673653142637321975391955100711368073708641745524
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008685513 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x7c6cf284, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10008685513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```