CSRNG Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	25.602us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	61.203us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	109.107us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	29.000s	1.784ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	151.398us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	113.902us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	109.107us	20	20	100.00
		csrng_csr_aliasing	9.000s	151.398us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	27.000s	1.397ms	200	200	100.00
V2	alerts	csrng_alert	44.000s	3.784ms	500	500	100.00
V2	err	csrng_err	7.000s	21.852us	500	500	100.00
V2	cmds	csrng_cmds	7.733m	45.157ms	50	50	100.00
V2	life cycle	csrng_cmds	7.733m	45.157ms	50	50	100.00
V2	stress_all	csrng_stress_all	28.517m	107.264ms	49	50	98.00
V2	intr_test	csrng_intr_test	5.000s	49.905us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	215.270us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	758.706us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	758.706us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	61.203us	5	5	100.00
		csrng_csr_rw	6.000s	109.107us	20	20	100.00
		csrng_csr_aliasing	9.000s	151.398us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	339.614us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	61.203us	5	5	100.00
		csrng_csr_rw	6.000s	109.107us	20	20	100.00
		csrng_csr_aliasing	9.000s	151.398us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	339.614us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	9.000s	288.318us	5	5	100.00
		csrng_tl_intg_err	22.000s	737.447us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	114.441us	50	50	100.00
		csrng_csr_rw	6.000s	109.107us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	44.000s	3.784ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	28.517m	107.264ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	44.000s	3.784ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	28.517m	107.264ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	44.000s	3.784ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	22.000s	737.447us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
		csrng_sec_cm	9.000s	288.318us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	27.000s	1.397ms	200	200	100.00
		csrng_err	7.000s	21.852us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.350m	3.193ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1619	1630	99.33

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.73	98.58	96.56	99.91	97.30	92.02	100.00	97.19	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.8799506040054977221819182625877543864594792273419835792777924580665361727242
      Line 130, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 907036930 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 907036930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.94872840560050332431318602446792695594397866608808668512018155507051515967398
      Line 101, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 274344980 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 274344980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
  • Test csrng_stress_all has 1 failures.

    • 4.csrng_stress_all.24844233903654538703767465057465211985215128779772393897325143019257110608791
      Line 138, in log /nightly/runs/scratch/master/csrng-sim-xcelium/4.csrng_stress_all/latest/run.log

        UVM_ERROR @ 10647359610 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 10647359610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---