EDN Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.480s 28.764us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.200s 53.748us 5 5 100.00
V1 csr_rw edn_csr_rw 2.180s 17.830us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.920s 346.292us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.800s 155.836us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.630s 26.294us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.180s 17.830us 20 20 100.00
edn_csr_aliasing 2.800s 155.836us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 52.240s 2.308ms 300 300 100.00
V2 csrng_commands edn_genbits 52.240s 2.308ms 300 300 100.00
V2 genbits edn_genbits 52.240s 2.308ms 300 300 100.00
V2 interrupts edn_intr 2.790s 20.102us 50 50 100.00
V2 alerts edn_alert 2.790s 43.521us 200 200 100.00
V2 errs edn_err 2.730s 28.281us 100 100 100.00
V2 disable edn_disable 2.260s 27.592us 50 50 100.00
edn_disable_auto_req_mode 2.530s 27.593us 50 50 100.00
V2 stress_all edn_stress_all 7.740s 301.558us 50 50 100.00
V2 intr_test edn_intr_test 2.290s 19.630us 50 50 100.00
V2 alert_test edn_alert_test 2.580s 31.633us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.060s 178.460us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.060s 178.460us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.200s 53.748us 5 5 100.00
edn_csr_rw 2.180s 17.830us 20 20 100.00
edn_csr_aliasing 2.800s 155.836us 5 5 100.00
edn_same_csr_outstanding 2.640s 40.885us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.200s 53.748us 5 5 100.00
edn_csr_rw 2.180s 17.830us 20 20 100.00
edn_csr_aliasing 2.800s 155.836us 5 5 100.00
edn_same_csr_outstanding 2.640s 40.885us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.140s 1.172ms 5 5 100.00
edn_tl_intg_err 3.730s 627.984us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.080s 50.564us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.790s 43.521us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.140s 1.172ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.140s 1.172ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.140s 1.172ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.140s 1.172ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.790s 43.521us 200 200 100.00
edn_sec_cm 9.140s 1.172ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.790s 43.521us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.730s 627.984us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.673m 25.825ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.67 98.32 94.23 97.02 91.28 96.33 99.78 92.75

Failure Buckets