ENTROPY_SRC Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 29.078us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 18.899us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 51.900us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 805.934us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 211.507us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 118.674us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 51.900us 20 20 100.00
entropy_src_csr_aliasing 9.000s 211.507us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 29.078us 50 50 100.00
entropy_src_rng 5.450m 10.107ms 20 300 6.67
entropy_src_fw_ov 8.167m 20.076ms 176 300 58.67
V2 firmware_mode entropy_src_fw_ov 8.167m 20.076ms 176 300 58.67
V2 rng_mode entropy_src_rng 5.450m 10.107ms 20 300 6.67
V2 rng_max_rate entropy_src_rng_max_rate 8.167m 14.318ms 9 400 2.25
V2 health_checks entropy_src_rng 5.450m 10.107ms 20 300 6.67
V2 conditioning entropy_src_rng 5.450m 10.107ms 20 300 6.67
V2 interrupts entropy_src_rng 5.450m 10.107ms 20 300 6.67
entropy_src_intr 24.000s 511.812us 50 50 100.00
V2 alerts entropy_src_rng 5.450m 10.107ms 20 300 6.67
entropy_src_functional_alerts 7.000s 452.607us 50 50 100.00
V2 stress_all entropy_src_stress_all 7.467m 20.309ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 5.100m 10.023ms 975 1000 97.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 30.000s 1.046ms 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 16.971us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 55.302us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 321.710us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 321.710us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 18.899us 5 5 100.00
entropy_src_csr_rw 5.000s 51.900us 20 20 100.00
entropy_src_csr_aliasing 9.000s 211.507us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 89.904us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 18.899us 5 5 100.00
entropy_src_csr_rw 5.000s 51.900us 20 20 100.00
entropy_src_csr_aliasing 9.000s 211.507us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 89.904us 20 20 100.00
V2 TOTAL 1519 2340 64.91
V2S tl_intg_err entropy_src_sec_cm 6.000s 106.999us 5 5 100.00
entropy_src_tl_intg_err 7.000s 195.471us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.450m 10.107ms 20 300 6.67
entropy_src_cfg_regwen 6.000s 18.599us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.450m 10.107ms 20 300 6.67
V2S sec_cm_config_redun entropy_src_rng 5.450m 10.107ms 20 300 6.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.450m 10.107ms 20 300 6.67
entropy_src_fw_ov 8.167m 20.076ms 176 300 58.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.100m 10.023ms 975 1000 97.50
entropy_src_sec_cm 6.000s 106.999us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.100m 10.023ms 975 1000 97.50
entropy_src_sec_cm 6.000s 106.999us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.450m 10.107ms 20 300 6.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 5.100m 10.023ms 975 1000 97.50
entropy_src_sec_cm 6.000s 106.999us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.100m 10.023ms 975 1000 97.50
entropy_src_sec_cm 6.000s 106.999us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.100m 10.023ms 975 1000 97.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 452.607us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 195.471us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.300m 11.069ms 4 50 8.00
V3 TOTAL 4 50 8.00
TOTAL 1703 2570 66.26

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.11 98.13 95.27 98.32 95.41 96.59 96.88 91.01 86.87

Failure Buckets