HMAC Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.800s	3.869ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.350s	20.476us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.280s	52.872us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.600s	7.504ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.420s	572.196us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.221m	49.096ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.280s	52.872us	20	20	100.00
		hmac_csr_aliasing	9.420s	572.196us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.166m	4.297ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.509m	3.380ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.178m	13.661ms	30	30	100.00
		hmac_test_sha384_vectors	9.041m	31.157ms	75	75	100.00
		hmac_test_sha512_vectors	9.029m	59.233ms	75	75	100.00
		hmac_test_hmac256_vectors	17.180s	841.853us	50	50	100.00
		hmac_test_hmac384_vectors	16.540s	1.785ms	60	60	100.00
		hmac_test_hmac512_vectors	21.640s	1.106ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	37.450s	5.445ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	23.674m	29.824ms	10	10	100.00
V2	error	hmac_error	2.078m	35.107ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.658m	30.481ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.800s	3.869ms	10	10	100.00
		hmac_long_msg	1.166m	4.297ms	10	10	100.00
		hmac_back_pressure	1.509m	3.380ms	25	25	100.00
		hmac_datapath_stress	23.674m	29.824ms	10	10	100.00
		hmac_burst_wr	37.450s	5.445ms	50	50	100.00
		hmac_stress_all	54.468m	1.177s	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.800s	3.869ms	10	10	100.00
		hmac_long_msg	1.166m	4.297ms	10	10	100.00
		hmac_back_pressure	1.509m	3.380ms	25	25	100.00
		hmac_datapath_stress	23.674m	29.824ms	10	10	100.00
		hmac_wipe_secret	2.658m	30.481ms	10	10	100.00
		hmac_test_sha256_vectors	4.178m	13.661ms	30	30	100.00
		hmac_test_sha384_vectors	9.041m	31.157ms	75	75	100.00
		hmac_test_sha512_vectors	9.029m	59.233ms	75	75	100.00
		hmac_test_hmac256_vectors	17.180s	841.853us	50	50	100.00
		hmac_test_hmac384_vectors	16.540s	1.785ms	60	60	100.00
		hmac_test_hmac512_vectors	21.640s	1.106ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.800s	3.869ms	10	10	100.00
		hmac_long_msg	1.166m	4.297ms	10	10	100.00
		hmac_back_pressure	1.509m	3.380ms	25	25	100.00
		hmac_datapath_stress	23.674m	29.824ms	10	10	100.00
		hmac_burst_wr	37.450s	5.445ms	50	50	100.00
		hmac_error	2.078m	35.107ms	10	10	100.00
		hmac_wipe_secret	2.658m	30.481ms	10	10	100.00
		hmac_test_sha256_vectors	4.178m	13.661ms	30	30	100.00
		hmac_test_sha384_vectors	9.041m	31.157ms	75	75	100.00
		hmac_test_sha512_vectors	9.029m	59.233ms	75	75	100.00
		hmac_test_hmac256_vectors	17.180s	841.853us	50	50	100.00
		hmac_test_hmac384_vectors	16.540s	1.785ms	60	60	100.00
		hmac_test_hmac512_vectors	21.640s	1.106ms	75	75	100.00
		hmac_stress_all	54.468m	1.177s	50	50	100.00
V2	stress_all	hmac_stress_all	54.468m	1.177s	50	50	100.00
V2	alert_test	hmac_alert_test	2.140s	13.405us	50	50	100.00
V2	intr_test	hmac_intr_test	2.160s	26.522us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.360s	2.802ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.360s	2.802ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.350s	20.476us	5	5	100.00
		hmac_csr_rw	2.280s	52.872us	20	20	100.00
		hmac_csr_aliasing	9.420s	572.196us	5	5	100.00
		hmac_same_csr_outstanding	3.780s	386.150us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.350s	20.476us	5	5	100.00
		hmac_csr_rw	2.280s	52.872us	20	20	100.00
		hmac_csr_aliasing	9.420s	572.196us	5	5	100.00
		hmac_same_csr_outstanding	3.780s	386.150us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.610s	185.020us	5	5	100.00
		hmac_tl_intg_err	6.250s	270.347us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.250s	270.347us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.800s	3.869ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.280s	137.692us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	12.752m	303.019ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.080s	275.748us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.06	100.00	97.14	100.00	100.00	100.00	100.00	47.27