I2C Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.510m	8.036ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	39.420s	9.299ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.210s	21.360us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.220s	83.671us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.040s	921.665us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.460s	115.390us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.760s	31.225us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.220s	83.671us	20	20	100.00
		i2c_csr_aliasing	3.460s	115.390us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	8.810s	2.003ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	57.694m	53.454ms	13	50	26.00
V2	host_maxperf	i2c_host_perf	39.760m	48.115ms	48	50	96.00
V2	host_override	i2c_host_override	2.200s	28.205us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.290m	5.233ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.792m	9.307ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.780s	577.532us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.700s	750.382us	50	50	100.00
		i2c_host_fifo_reset_rx	12.790s	219.359us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.619m	7.285ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	38.960s	855.667us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.680s	903.595us	18	50	36.00
V2	target_glitch	i2c_target_glitch	13.590s	2.351ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	21.407m	61.153ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	9.260s	3.843ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.135m	1.884ms	50	50	100.00
		i2c_target_intr_smoke	11.150s	1.160ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.370s	288.552us	50	50	100.00
		i2c_target_fifo_reset_tx	3.820s	300.862us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	18.342m	64.140ms	50	50	100.00
		i2c_target_stress_rd	1.135m	1.884ms	50	50	100.00
		i2c_target_intr_stress_wr	10.225m	31.353ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.760s	7.310ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.906m	4.162ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	10.470s	4.901ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	34.790s	10.100ms	24	50	48.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.880s	2.833ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.390s	636.975us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	39.760m	48.115ms	48	50	96.00
		i2c_host_perf_precise	14.156m	24.341ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	38.960s	855.667us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	8.620s	478.372us	45	50	90.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.300s	1.059ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.130s	1.085ms	50	50	100.00
		i2c_target_nack_txstretch	3.500s	162.219us	31	50	62.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	26.500s	641.228us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.950s	2.896ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.170s	24.411us	50	50	100.00
V2	intr_test	i2c_intr_test	2.250s	50.353us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.250s	565.311us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.250s	565.311us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.210s	21.360us	5	5	100.00
		i2c_csr_rw	2.220s	83.671us	20	20	100.00
		i2c_csr_aliasing	3.460s	115.390us	5	5	100.00
		i2c_same_csr_outstanding	2.650s	588.756us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.210s	21.360us	5	5	100.00
		i2c_csr_rw	2.220s	83.671us	20	20	100.00
		i2c_csr_aliasing	3.460s	115.390us	5	5	100.00
		i2c_same_csr_outstanding	2.650s	588.756us	19	20	95.00
V2		TOTAL			1660	1792	92.63
V2S	tl_intg_err	i2c_tl_intg_err	3.310s	144.667us	20	20	100.00
		i2c_sec_cm	2.580s	96.159us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.310s	144.667us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	50.490s	1.577ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.370s	800.843us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	42.760s	8.285ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1840	2042	90.11

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.80	97.19	89.48	74.17	71.43	94.04	98.52	89.75

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 43 failures:

Test i2c_host_stress_all has 28 failures.

0.i2c_host_stress_all.80000824128357289141077221307208110789555457207079129949057043628002177809431
Line 189, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 23578037847 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3024128

1.i2c_host_stress_all.48211768154100226735601589423626880237708220324891966637474153328464144152933
Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 51768704427 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @12141268

... and 26 more failures.

Test i2c_host_mode_toggle has 15 failures.

0.i2c_host_mode_toggle.83327939982805921858697365808339309424446080464401232152877487683401855091084
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 110714069 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @49621

1.i2c_host_mode_toggle.75489062917675550607962063395798647199566704314291956332693180778907685779853
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 190065823 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @54153

... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
- Test i2c_target_unexp_stop has 30 failures.
  - 0.i2c_target_unexp_stop.32491240941012419424197363228073470640566545785348250746766589836141989190705
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 421026786 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 27 [0x1b])
  UVM_INFO @ 421026786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.95272091495211507002318262288962536103780044172696840941567976474669251882594
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  52398028 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 127 [0x7f])
  UVM_INFO @  52398028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 6.i2c_target_stress_all_with_rand_reset.7375200676231173308917457142332149466818472180176065487163297815048999813680
    Line 103, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1036368367 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 207 [0xcf])
  UVM_INFO @ 1036368367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
- Test i2c_target_hrst has 26 failures.
  - 0.i2c_target_hrst.75967155539841696811632408170440301539836728244700952369580390121699984049789
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10231352511 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10231352511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_hrst.75516873303995866660568540512124368006326145583771904445240716524732292688389
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10498811184 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10498811184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
- Test i2c_target_nack_txstretch has 19 failures.
  - 0.i2c_target_nack_txstretch.100490924982148955235658799786012291595518916519103596984738775752611490237215
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 352040842 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 352040842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_nack_txstretch.84601609545682289786469179472694713039435050840551837986238839750699164329456
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 3153032517 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 3153032517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 17 failures:

Test i2c_host_mode_toggle has 16 failures.

7.i2c_host_mode_toggle.36197209523308708726521581597650502183748978200299836436325061143855861958438
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 105573081 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

13.i2c_host_mode_toggle.41655676735596101808916310308381980408960730495177008461489506444462906469927
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 117784959 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 14 more failures.

Test i2c_host_perf has 1 failures.

31.i2c_host_perf.83479831339220990945791797234829834421419164827935705258301228868451728073783
Line 77, in log /nightly/runs/scratch/master/i2c-sim-vcs/31.i2c_host_perf/latest/run.log

  UVM_ERROR @ 608772700 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 1.i2c_target_unexp_stop.78354364124830604923034320951404206405307563341447353948267032032463022354536
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 257057861 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 257057861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.84700911157256754668982404911734954742941077348441187210562048324718769706524
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 805991153 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 805991153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

0.i2c_host_stress_all_with_rand_reset.48802952432929068433133574124723533355079888954425841779107386117227519464522
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 747189753 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 747189753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.82631654191947040435003774035525661105459807898452995648025564472012343748142
Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 734226611 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 734226611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

1.i2c_target_stress_all_with_rand_reset.104090434627952074642985337610639554410202599630375735354356565269970065580991
Line 149, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2355983924 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2355983924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.20793390916868604076354548824642462851809371519601991811996717333808302634645
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3168924650 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3168924650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
- Test i2c_target_tx_stretch_ctrl has 5 failures.
  - 3.i2c_target_tx_stretch_ctrl.10615499807659813396621369128201871527300556422969446210501476713234241458077
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 10.i2c_target_tx_stretch_ctrl.74728124813750643518870906657592949928336955726964815641425549228905379019154
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 3 more failures.
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 6.i2c_target_fifo_watermarks_tx.43706297708364725215163886577471749341788681215330303337132911790272508273049
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
- Test i2c_target_stretch has 6 failures.
  - 4.i2c_target_stretch.105273369344176122640360925616886978922157085490300588278808625929895225736433
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001076496 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001076496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.i2c_target_stretch.30637142763571438352697363715200174550682455353295934001054519724409444098701
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/28.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10005611558 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10005611558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

38.i2c_host_stress_all.17689050090854689120219262008462271237820664792159787668001378323070195178010
Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 53439643961 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1964620

45.i2c_host_stress_all.75029341084324395988012991713521163793746184112337384656129450096804364366759
Line 154, in log /nightly/runs/scratch/master/i2c-sim-vcs/45.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 51258793283 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4638484

... and 3 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:

Test i2c_target_unexp_stop has 4 failures.

19.i2c_target_unexp_stop.22620396872808328134780640818504068033153907314228498856298426883504176884001
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 800843162 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 800843162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.i2c_target_unexp_stop.15818213170413141695790381441928223186699854815054078602169064604823069600134
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 126997327 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 126997327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 0.i2c_target_stress_all_with_rand_reset.95309211423401947833660306115964625544841160563784350807119166948935622751448
    Line 119, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8285146753 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8285146753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_stress_all_with_rand_reset.50442489710523715829753881787648986631716175475521912894166133123958230826536
    Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16488807501 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16488807501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 3 failures:
- Test i2c_host_stress_all has 3 failures.
  - 22.i2c_host_stress_all.2313836961271075715200601329146197624987436561618138317229588759746809422609
    Log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 27.i2c_host_stress_all.111971594205672015250879579968454862985000513263099452646407181419216818855031
    Log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 3.i2c_target_stress_all.80180297570990852390618300807051171942340802724161760257948448385292996466083
    Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 58358317449 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 58358317449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.i2c_target_stress_all.99832860119339477878322848227638529049582631322167718935604743501077690698130
    Line 76, in log /nightly/runs/scratch/master/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 23602693065 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 23602693065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_host_stress_all_with_rand_reset.96710727021746790026200029046390955149199428078775798269700170639316113088533
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1178384733 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (6 [0x6] vs 3 [0x3])
  UVM_INFO @ 1178384733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 13.i2c_same_csr_outstanding.80645312705999960794867022764261296569420288063620843083370560472674047807404
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  57099388 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  57099388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=68) has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 16.i2c_host_perf.22985278483160528912925919348346427992590773555923618115480842148847839946291
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 13158877891 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x425f5f14, Comparison=CompareOpEq, exp_data=0x0, call_count=68)
  UVM_INFO @ 13158877891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 16.i2c_host_stress_all.71633737883849400130080049022869968474287311992133026219918499426700937730424
    Line 119, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 27278323114 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 45.i2c_target_bad_addr.50723042445621229684121006445034644185288049211520418509066278883331084566067
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/45.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 48.i2c_host_mode_toggle.44847773600654429197273655812317311826717673240205916024765596308282239477144
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/48.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```