KEYMGR Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	31.390s	4.303ms	50	50	100.00
V1	random	keymgr_random	1.005m	10.269ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.420s	28.744us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.850s	182.191us	18	20	90.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.440s	7.179ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	9.760s	6.030ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.150s	25.142us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.850s	182.191us	18	20	90.00
		keymgr_csr_aliasing	9.760s	6.030ms	4	5	80.00
V1		TOTAL			149	155	96.13
V2	cfgen_during_op	keymgr_cfg_regwen	1.137m	12.119ms	50	50	100.00
V2	sideload	keymgr_sideload	53.660s	7.158ms	50	50	100.00
		keymgr_sideload_kmac	30.950s	2.990ms	50	50	100.00
		keymgr_sideload_aes	54.440s	8.959ms	50	50	100.00
		keymgr_sideload_otbn	54.540s	7.577ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	37.300s	7.432ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	28.320s	3.190ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.140s	247.207us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.451m	12.199ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	48.970s	2.104ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	14.850s	665.850us	50	50	100.00
V2	stress_all	keymgr_stress_all	6.483m	83.404ms	46	50	92.00
V2	intr_test	keymgr_intr_test	2.340s	9.266us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.830s	86.649us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.820s	117.642us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.820s	117.642us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.420s	28.744us	5	5	100.00
		keymgr_csr_rw	2.850s	182.191us	18	20	90.00
		keymgr_csr_aliasing	9.760s	6.030ms	4	5	80.00
		keymgr_same_csr_outstanding	5.100s	344.903us	17	20	85.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.420s	28.744us	5	5	100.00
		keymgr_csr_rw	2.850s	182.191us	18	20	90.00
		keymgr_csr_aliasing	9.760s	6.030ms	4	5	80.00
		keymgr_same_csr_outstanding	5.100s	344.903us	17	20	85.00
V2		TOTAL			731	740	98.78
V2S	sec_cm_additional_check	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
		keymgr_tl_intg_err	9.100s	417.573us	16	20	80.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.380s	149.328us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.380s	149.328us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.380s	149.328us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.380s	149.328us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.740s	854.768us	12	20	60.00
V2S	prim_count_check	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.100s	417.573us	16	20	80.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.380s	149.328us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.137m	12.119ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.005m	10.269ms	50	50	100.00
		keymgr_csr_rw	2.850s	182.191us	18	20	90.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.005m	10.269ms	50	50	100.00
		keymgr_csr_rw	2.850s	182.191us	18	20	90.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.005m	10.269ms	50	50	100.00
		keymgr_csr_rw	2.850s	182.191us	18	20	90.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	28.320s	3.190ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	48.970s	2.104ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	48.970s	2.104ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.005m	10.269ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	17.290s	8.407ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	24.490s	725.853us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	28.320s	3.190ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	24.490s	725.853us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	24.490s	725.853us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	24.490s	725.853us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	28.860s	1.680ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	24.490s	725.853us	50	50	100.00
V2S		TOTAL			153	165	92.73
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.190s	633.054us	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1064	1110	95.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.10	98.18	98.51	100.00	99.01	98.63	91.16

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 21 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 8 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.29702193680574063426310546480198721588475146019879061175291467790190149766776
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  10305030 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  10305030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_shadow_reg_errors_with_csr_rw.103192722808282565025728845544076702802496082889791442416294723440657831025548
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  27515386 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  27515386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_same_csr_outstanding has 3 failures.

0.keymgr_same_csr_outstanding.36590189292927894666008394885870562171827609741274384463798458504585049927541
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @  37691948 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @  37691948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.keymgr_same_csr_outstanding.73579957042347165785433418172460234728911178434577386708664201582268805511633
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  26399428 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  26399428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_tl_intg_err has 4 failures.

1.keymgr_tl_intg_err.61166354725275335286493015732901791794460336528073794605114246563932941303753
Line 93, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  27245094 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  27245094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_tl_intg_err.94555439080570385928341841626672078392912475973904195770714491387025768939712
Line 138, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  74175511 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  74175511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_csr_aliasing has 1 failures.

1.keymgr_csr_aliasing.90268850112224905956703541405686045341313947227747409339781855636378507698529
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  68589956 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  68589956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_bit_bash has 1 failures.

3.keymgr_csr_bit_bash.9556022272848535360247802131834804757038441926504313100233478195028503843102
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @ 2325105102 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @ 2325105102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 2.keymgr_stress_all_with_rand_reset.22656025712943552056164340954185243890681167596262590463302936613550876961533
    Line 283, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2105233050 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2105233050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.69590301542362246232794536307740379432541996914516276492590154808316173475407
    Line 239, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171526792 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 171526792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_hwsw_invalid_input has 1 failures.

4.keymgr_hwsw_invalid_input.744326728369667938092927357883404909705420388744461509891041880931978647317
Line 172, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @  20559684 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  20559684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all_with_rand_reset has 2 failures.

17.keymgr_stress_all_with_rand_reset.20168119725313255883135140116392204561740558941042634499755541846815645674102
Line 1703, in log /nightly/runs/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 397103305 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 397103305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.keymgr_stress_all_with_rand_reset.92098597175774258475051386461113471444402093142685671709876036998818325647025
Line 1756, in log /nightly/runs/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 777418402 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 777418402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

34.keymgr_kmac_rsp_err.75354597541595656169271752916356592977013142132841556553588665084020695732740
Line 163, in log /nightly/runs/scratch/master/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  52777821 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  52777821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

34.keymgr_stress_all.36367516381747574119145162801485013173024794401882924580942388413351199247299
Line 3458, in log /nightly/runs/scratch/master/keymgr-sim-vcs/34.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1094884802 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 1094884802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 8.keymgr_stress_all.34677873177457907657508165590887633571544303648541670111665270387826811476283
    Line 4783, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 9028153220 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (4 [0x4] vs 6 [0x6])
  UVM_INFO @ 9028153220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Sealing Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

27.keymgr_stress_all.46445555593627456857658048459655133940900416949086024718493525332008092951269
Line 1812, in log /nightly/runs/scratch/master/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2096115062 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (11365547683488815454896793317660493363955753432972610435811535992492926508649270039118510843544133272190246626846413990719231669951073753981901998894389749 [0xd901a3cd89a474cbdd6754dd8e605646fb9b0e3362332ff0205c4241c4fc8b0df4d2171f01aead10fd56e8dff57715c00aab31d6abca4a83fc168847601c99f5] vs 11365547683488815454896793317660493363955753432972610435811535992492926508649270039118510843544133272190246626846413990719231669951073753981901998894389749 [0xd901a3cd89a474cbdd6754dd8e605646fb9b0e3362332ff0205c4241c4fc8b0df4d2171f01aead10fd56e8dff57715c00aab31d6abca4a83fc168847601c99f5]) KMAC key at state StOwnerKey for Sealing Kmac
  UVM_INFO @ 2096115062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 49.keymgr_stress_all.11027643823250659113394462555511462148943421967277748673289778539058790913223
    Line 1004, in log /nightly/runs/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1237954235 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @ 1237954235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```