KMAC/MASKED Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.421m	16.893ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.430s	84.512us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.680s	51.784us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.070s	2.948ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.890s	2.060ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.930s	129.493us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.680s	51.784us	20	20	100.00
		kmac_csr_aliasing	8.890s	2.060ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.410s	13.207us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.910s	43.420us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.431m	462.344ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.279m	175.021ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.932m	202.146ms	5	5	100.00
		kmac_test_vectors_sha3_256	35.699m	91.215ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.882m	52.308ms	5	5	100.00
		kmac_test_vectors_sha3_512	23.380m	48.902ms	5	5	100.00
		kmac_test_vectors_shake_128	46.495m	447.498ms	5	5	100.00
		kmac_test_vectors_shake_256	32.976m	302.304ms	5	5	100.00
		kmac_test_vectors_kmac	4.860s	1.475ms	5	5	100.00
		kmac_test_vectors_kmac_xof	4.140s	381.458us	5	5	100.00
V2	sideload	kmac_sideload	9.106m	92.959ms	50	50	100.00
V2	app	kmac_app	7.792m	19.915ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.250m	43.100ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.421m	62.405ms	50	50	100.00
V2	error	kmac_error	7.689m	22.287ms	49	50	98.00
V2	key_error	kmac_key_error	21.660s	9.853ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.300s	1.631ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.820s	6.454ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.200s	2.198ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.140m	21.607ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.350s	7.565ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.684m	144.159ms	49	50	98.00
V2	intr_test	kmac_intr_test	2.290s	34.300us	50	50	100.00
V2	alert_test	kmac_alert_test	2.360s	57.755us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.300s	1.082ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.300s	1.082ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.430s	84.512us	5	5	100.00
		kmac_csr_rw	2.680s	51.784us	20	20	100.00
		kmac_csr_aliasing	8.890s	2.060ms	5	5	100.00
		kmac_same_csr_outstanding	3.530s	103.634us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.430s	84.512us	5	5	100.00
		kmac_csr_rw	2.680s	51.784us	20	20	100.00
		kmac_csr_aliasing	8.890s	2.060ms	5	5	100.00
		kmac_same_csr_outstanding	3.530s	103.634us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.000s	233.678us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.000s	233.678us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.000s	233.678us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.000s	233.678us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.380s	1.624ms	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	2.750m	59.220ms	5	5	100.00
		kmac_tl_intg_err	6.120s	366.359us	12	20	60.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.120s	366.359us	12	20	60.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.350s	7.565ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.421m	16.893ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.106m	92.959ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.000s	233.678us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.750m	59.220ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.750m	59.220ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.750m	59.220ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.421m	16.893ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.350s	7.565ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.750m	59.220ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.466m	8.434ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.421m	16.893ms	50	50	100.00
V2S		TOTAL			62	75	82.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.775m	5.069ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			923	940	98.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.84	99.09	94.50	99.89	76.06	97.09	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 13 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

0.kmac_shadow_reg_errors_with_csr_rw.24943183978178893483615289455174765822206921449602857913387850615477680228018
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  24802021 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  24802021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.56554123062079089849219871694459143480358096311466523519085191102013541470277
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @ 121388440 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @ 121388440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_tl_intg_err has 8 failures.

1.kmac_tl_intg_err.59095032564902294857400535926356312385674461388792779707244186515287190464843
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  38670888 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  38670888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_tl_intg_err.64065282989722726042963964150893787959185489327030747802985490972373981198026
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  64689793 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  64689793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.108675233242170520990384197052800937881942957509404699792566661246839931150320
    Line 138, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7579430141 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7579430141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.38300117408545435470433806819458719812727416494006354672163394719459731533825
    Line 101, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 136164255 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 136164255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 36.kmac_error.86932198876173025632988553502919533963910279500268970734483807591804409740881
    Line 210, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/36.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 38.kmac_stress_all.44616007472254067415865640456013061419910646902033114077819775587983411103771
    Line 276, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 14456335756 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 14456335756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```