KMAC/UNMASKED Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.094m	42.453ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.570s	21.855us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.690s	28.018us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	24.170s	3.005ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.950s	1.595ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.080s	261.183us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.690s	28.018us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.595ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.210s	35.456us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.000s	378.772us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.942m	582.147ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.920m	172.173ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.466m	394.449ms	5	5	100.00
		kmac_test_vectors_sha3_256	32.893m	619.504ms	5	5	100.00
		kmac_test_vectors_sha3_384	32.160s	23.933ms	5	5	100.00
		kmac_test_vectors_sha3_512	13.931m	188.528ms	5	5	100.00
		kmac_test_vectors_shake_128	29.912m	139.703ms	5	5	100.00
		kmac_test_vectors_shake_256	5.957m	93.197ms	5	5	100.00
		kmac_test_vectors_kmac	4.210s	1.333ms	5	5	100.00
		kmac_test_vectors_kmac_xof	3.710s	127.096us	5	5	100.00
V2	sideload	kmac_sideload	9.616m	305.618ms	50	50	100.00
V2	app	kmac_app	6.049m	29.009ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.355m	87.802ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.854m	77.935ms	50	50	100.00
V2	error	kmac_error	6.472m	45.759ms	50	50	100.00
V2	key_error	kmac_key_error	15.260s	3.743ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.097m	10.036ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.940s	3.491ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.190s	5.435ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	56.460s	45.225ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.360s	3.785ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.202m	91.547ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.320s	22.856us	50	50	100.00
V2	alert_test	kmac_alert_test	2.340s	184.529us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.620s	1.401ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.620s	1.401ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.570s	21.855us	5	5	100.00
		kmac_csr_rw	2.690s	28.018us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.595ms	5	5	100.00
		kmac_same_csr_outstanding	3.930s	369.719us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.570s	21.855us	5	5	100.00
		kmac_csr_rw	2.690s	28.018us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.595ms	5	5	100.00
		kmac_same_csr_outstanding	3.930s	369.719us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.330s	73.574us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.330s	73.574us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.330s	73.574us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.330s	73.574us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.820s	104.899us	14	20	70.00
V2S	tl_intg_err	kmac_sec_cm	1.085m	24.540ms	5	5	100.00
		kmac_tl_intg_err	6.360s	349.143us	19	20	95.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.360s	349.143us	19	20	95.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.360s	3.785ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.094m	42.453ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.616m	305.618ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.330s	73.574us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.085m	24.540ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.085m	24.540ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.085m	24.540ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.094m	42.453ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.360s	3.785ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.085m	24.540ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.284m	49.524ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.094m	42.453ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.855m	25.005ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			913	940	97.13

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.02	97.17	94.42	100.00	75.21	95.98	99.35	95.98

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 7 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

5.kmac_shadow_reg_errors_with_csr_rw.44933545837152525474071688400090352943160182662760414666577835165871097405095
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  20854756 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  20854756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors_with_csr_rw.86246911565977366255093232460292601956197586108474114018350351571283741438194
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  16889339 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  16889339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_tl_intg_err has 1 failures.

9.kmac_tl_intg_err.37674827135467087736677501124148005505518993048625951752609585943056475904856
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  18697276 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  18697276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 0.kmac_sideload_invalid.24107149593046868479673604482826153506533452961628047641168663706323193299319
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10009813308 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x282f7000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10009813308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.kmac_sideload_invalid.42131373823968821570855890127689998969928865647267995115202093082742601762950
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10036028540 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3728c000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10036028540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 4.kmac_stress_all_with_rand_reset.49648310130044030221839969255548022316070936207756359502399136139292544154112
    Line 275, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6325652378 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6325652378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.20456005913187235543982352267882172602424699157618985031864214464817755917453
    Line 133, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6585277683 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6585277683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 7.kmac_sideload_invalid.51989557182743916324119900689818704764263583171581260028961091742953558786929
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10041708505 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb54a5000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10041708505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.kmac_sideload_invalid.2893416159670599490383216305291772605856119184075415526802007090651011417795
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10098679384 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5f654000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10098679384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 9.kmac_sideload_invalid.93650471164820213224568173993788766668498988723989579239839731066499268040217
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10129660704 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7425a000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10129660704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.kmac_sideload_invalid.57608889156141442850289709007687869917475169586117801362635829364160105595604
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10036143267 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd43bc000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10036143267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 22.kmac_sideload_invalid.10364239999232282969186062904778429577509115694927431215725228542558041931402
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10782959225 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x57b27000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10782959225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 37.kmac_sideload_invalid.22096386288082841985146281996535152075468236525418308664898969322469606768678
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 11278092278 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xafde1000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 11278092278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 1.kmac_stress_all_with_rand_reset.105622141645513477108541719587354811846708624949782070733445258830025162483126
    Line 99, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5498992564 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5498992564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 2.kmac_sideload_invalid.40067903083187413176511094256356176334285470654022348885501283345243653966286
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10199335516 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x20f97000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10199335516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 23.kmac_sideload_invalid.24395557391912843633850210451501587753476089211226892248864501402516297099981
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10311091319 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2c23c000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
  UVM_INFO @ 10311091319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 29.kmac_sideload_invalid.38988802123689659391309766222455414368565763712436904237760866140447836303828
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10147661926 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x89ad5000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10147661926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```