OTBN Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: `77a9e5b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	128.856us	1	1	100.00
V1	single_binary	otbn_single	2.000m	1.592ms	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	30.000s	19.032us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	24.983us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	355.267us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	247.068us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	119.064us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	24.983us	20	20	100.00
		otbn_csr_aliasing	8.000s	247.068us	5	5	100.00
V1	mem_walk	otbn_mem_walk	48.000s	604.345us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	45.000s	123.381us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	1.133m	312.880us	10	10	100.00
V2	multi_error	otbn_multi_err	57.000s	460.814us	1	1	100.00
V2	back_to_back	otbn_multi	7.583m	1.794ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.350m	201.085us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.583m	672.525us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	24.212us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	40.000s	134.758us	10	10	100.00
V2	alert_test	otbn_alert_test	14.000s	29.316us	50	50	100.00
V2	intr_test	otbn_intr_test	47.000s	25.740us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	52.000s	205.256us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	52.000s	205.256us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	30.000s	19.032us	5	5	100.00
		otbn_csr_rw	9.000s	24.983us	20	20	100.00
		otbn_csr_aliasing	8.000s	247.068us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	15.853us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	30.000s	19.032us	5	5	100.00
		otbn_csr_rw	9.000s	24.983us	20	20	100.00
		otbn_csr_aliasing	8.000s	247.068us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	15.853us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	15.000s	27.528us	10	10	100.00
		otbn_dmem_err	19.000s	265.317us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	58.813us	5	5	100.00
		otbn_controller_ispr_rdata_err	34.000s	121.866us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	62.999us	5	5	100.00
		otbn_urnd_err	13.000s	30.688us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	34.692us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	34.287us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	59.140us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
		otbn_tl_intg_err	1.100m	673.052us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.100m	93.242us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	128.856us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	265.317us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	27.528us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.100m	673.052us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.583m	672.525us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	27.528us	10	10	100.00
		otbn_dmem_err	19.000s	265.317us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	24.212us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	34.692us	5	5	100.00
		otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	27.528us	10	10	100.00
		otbn_dmem_err	19.000s	265.317us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	24.212us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	34.692us	5	5	100.00
		otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.583m	672.525us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	27.528us	10	10	100.00
		otbn_dmem_err	19.000s	265.317us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	24.212us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	34.692us	5	5	100.00
		otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	42.949us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	25.406us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	3.500m	835.371us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	3.500m	835.371us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	39.403us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	6.083m	1.675ms	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	112.829us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	112.829us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	15.802us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	7.583m	1.794ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	48.373us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.000m	1.592ms	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.583m	3.132ms	3	5	60.00
V2S		TOTAL			155	163	95.09
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.733m	1.574ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			566	585	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.06	99.58	95.12	99.71	93.17	93.58	100.00	97.50	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test otbn_stress_all_with_rand_reset has 8 failures.
  - 0.otbn_stress_all_with_rand_reset.114223939707438207859196543989800962833980319887487499768951186588064486389583
    Line 554, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1573882124 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1573882124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.otbn_stress_all_with_rand_reset.19370766253833514297791073981645164246770185144171035215831178651371018299266
    Line 173, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3453108523 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3453108523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 3 failures:

Test otbn_passthru_mem_tl_intg_err has 2 failures.

1.otbn_passthru_mem_tl_intg_err.40480514356419435770119487089993981802728343786213895740513000268282708552302
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  40099243 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  40099243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_passthru_mem_tl_intg_err.65595463856906885659105349466318601600787428639201897172058641028486717692721
Line 97, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  50194884 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  50194884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_single has 1 failures.

78.otbn_single.107518150713778294350109582661694389541486643088809360754452486761028515105177
Line 105, in log /nightly/runs/scratch/master/otbn-sim-xcelium/78.otbn_single/latest/run.log

  UVM_FATAL @  28024945 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  28024945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.81460846197624682240894918333742318974973718059568150653093694687854431181937
Line 95, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 26646277 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 26646277 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  26646277 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  26646277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_cm.107926501029038881955725679629730809474854160286201006986323728909671394779526
Line 105, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 119244122 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 119244122 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 119244122 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 119244122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_sec_wipe_err has 2 failures.

2.otbn_sec_wipe_err.96301609303006820852667155953095958648227085867898774684851365919819324946504
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19754860 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19754860 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19754860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.otbn_sec_wipe_err.100840615601854331586337710170496088602391492466593699197337795747888759606355
Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29330407 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  29330407 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  29330407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 3.otbn_stress_all_with_rand_reset.96159861649995813505462860784569668369441098597744475757100351341912547461211
    Line 162, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 287763909 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 287763909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.otbn_stress_all_with_rand_reset.71009652875361776407837604526678476817686804689767246183271467429116857780998
    Line 266, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2322446624 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2322446624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:

Test otbn_partial_wipe has 1 failures.

3.otbn_partial_wipe.72525656284190320298458103663038589310303802594352156813994941566861105522534
Line 100, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 3351368 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
  UVM_ERROR @   3351368 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
  UVM_INFO @   3351368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 10.otbn_passthru_mem_tl_intg_err.110649894487071183674005883518605165404458238643849283618117839935760013641256
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/10.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   9878867 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   9878867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```