77a9e5b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 8.000s | 463.806us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 45.000s | 47.235us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 45.000s | 15.567us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 47.000s | 548.652us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 45.000s | 80.578us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 44.000s | 20.236us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 45.000s | 15.567us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 45.000s | 80.578us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 40.950m | 600.000ms | 28 | 50 | 56.00 |
| V2 | cnt_rollover | cnt_rollover | 1.300m | 2.169ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 32.649us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.834h | 1.409s | 19 | 50 | 38.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 28.156us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 45.000s | 14.409us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 45.000s | 70.478us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 45.000s | 70.478us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 45.000s | 47.235us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 45.000s | 15.567us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 45.000s | 80.578us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 44.000s | 109.138us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 45.000s | 47.235us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 45.000s | 15.567us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 45.000s | 80.578us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 44.000s | 109.138us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 340 | 84.41 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 45.000s | 285.958us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 118.699us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 45.000s | 285.958us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 3.200m | 6.604ms | 4 | 50 | 8.00 |
| V3 | TOTAL | 4 | 50 | 8.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.717m | 10.005ms | 34 | 50 | 68.00 | |
| TOTAL | 455 | 570 | 79.82 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.88 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 90.73 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 45 failures:
0.pattgen_stress_all_with_rand_reset.24886941288514466688039228868975512081967281565780519266714658074898149116925
Line 178, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2382285461 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2382314646 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2382314646 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 2382714646 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.42947661711408674503204350980713569568288012281974675149055566729291224310409
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 219237440 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 219247659 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 219247659 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 219347659 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 43 more failures.
Job timed out after * minutes has 30 failures:
2.pattgen_perf.69955426590125710699365630807770101358117061056269417349332977113678673066614
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
3.pattgen_perf.62964333777285783154109664164778861406520492600357130850904758991500196067305
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 13 more failures.
3.pattgen_stress_all.50564313108711345205623416774543640267299895392953898353550649231640961029973
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
6.pattgen_stress_all.94003308146825573375848917002931732051695104722239119270215720212255809216911
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 13 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 15 failures:
2.pattgen_stress_all.81351304081431507868642958413878992845902386599679706872129257455058538853861
Line 127, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 2685100509 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @10329
4.pattgen_stress_all.83424833377590887776968048587482066552503185190576514146696473373201973698713
Line 139, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 339408193 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10458
... and 13 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:
9.pattgen_perf.58410978735998780380724929751198674449967139410578513708410823792174891624036
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.pattgen_perf.20652885490749991207518125029718143801300488113531187122968135626908925304427
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/16.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
17.pattgen_stress_all.47106453510256755643652178717822169498211693047344230870488300968206726262777
Line 108, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
27.pattgen_inactive_level.94643161452073668542104400071342003785008437383260258800450857422807381686836
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002218674 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1fa89910, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002218674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.pattgen_inactive_level.8964781780623957251156005903877748452323017722808920980369678806631033939083
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002091625 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x37a6fe90, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002091625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
1.pattgen_inactive_level.15824097306534739612637707216432061096172738227361046235083090688814979478512
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010019041 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe5a2f3d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10010019041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.pattgen_inactive_level.28424846833947280641996702612859899535593088503937651897735864630641792911708
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10040032745 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe9843350, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10040032745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
2.pattgen_inactive_level.29885511209527391099201530030816963593709568153513223740018695737791419465172
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004012302 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2e008fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004012302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.pattgen_inactive_level.24512236836464744065474699877188116169592760939136561539615951367701715999705
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10018053185 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x424aef10, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10018053185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
11.pattgen_inactive_level.17464195378748359720280872468653031536984641833440325714254030992254386595545
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10529938100 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x314cb650, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10529938100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.pattgen_inactive_level.66096673770537975493731043561374944243903793147154194755512404156852095382219
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028274118 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x39138b50, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10028274118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 2 failures:
15.pattgen_inactive_level.5071830295487217670056333463462761905763154295441266222108640687494449985250
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10049883130 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x14daa9d0, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10049883130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.pattgen_inactive_level.57304118357760943243164618662104421915751301317385037993567306775390142106507
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10073756845 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x82141f10, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10073756845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
3.pattgen_inactive_level.84241061496238885072669869906244027104668812498119912392501358119893176117192
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10804322806 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1270cdd0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10804322806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
4.pattgen_stress_all_with_rand_reset.108824575210868890238319098319102643130337128710547789907110798328248061736307
Line 117, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 796778002 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
9.pattgen_inactive_level.53205064449730700906265001419588492281024028902310743204823511283418814919177
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015694497 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5cc1ff10, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10015694497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
26.pattgen_inactive_level.12707307578164283639962375546815474089539302369152144522497785449356553564768
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004845219 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xe664c1d0, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10004845219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
31.pattgen_inactive_level.86071637297218207507218927453321089314825779818319318821297512248607357711983
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10022901599 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb751a150, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10022901599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
34.pattgen_inactive_level.14161179978976946296813197441309355218034749269438914720434786603487597923920
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10258296138 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4c299f90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10258296138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---