ROM_CTRL/32KB Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.020s	309.904us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.580s	302.839us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.640s	168.957us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.960s	172.744us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.610s	305.409us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.860s	172.738us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.640s	168.957us	20	20	100.00
		rom_ctrl_csr_aliasing	6.610s	305.409us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.850s	132.156us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.770s	168.929us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	10.430s	183.439us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	26.340s	418.262us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.690s	316.810us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.550s	1.065ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	13.150s	241.517us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	13.150s	241.517us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.580s	302.839us	5	5	100.00
		rom_ctrl_csr_rw	7.640s	168.957us	20	20	100.00
		rom_ctrl_csr_aliasing	6.610s	305.409us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.480s	2.305ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.580s	302.839us	5	5	100.00
		rom_ctrl_csr_rw	7.640s	168.957us	20	20	100.00
		rom_ctrl_csr_aliasing	6.610s	305.409us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.480s	2.305ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	33.030s	869.372us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.260m	1.708ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.212m	465.883us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.260m	1.708ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.260m	1.708ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.260m	1.708ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.260m	1.708ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.020s	309.904us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.020s	309.904us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.020s	309.904us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.212m	465.883us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
		rom_ctrl_kmac_err_chk	14.690s	316.810us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.278m	20.204ms	5	20	25.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	33.030s	869.372us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.260m	1.708ms	5	5	100.00
V2S		TOTAL			50	65	76.92
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.352m	15.120ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			251	266	94.36

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.61	99.47	99.41	100.00	93.33	100.00	98.97	99.05

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 13 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 13 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.7022126302189331806723826992766859665571147438564558779622860297092191678012
      Line 73, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 638657428 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 638657428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.rom_ctrl_corrupt_sig_fatal_chk.59136529212620072968880052781487423171765743116299670593035120936168166799807
      Line 88, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1045054589 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 1045054589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.110512501088771540447315840205409025307901888862585803019726921687393598186440
      Line 93, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 593361766 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 593361766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(counter_lnt -> kmac_rom_vld_o)' has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 13.rom_ctrl_corrupt_sig_fatal_chk.83603340845577294001971713406785044218296963033908457839672073094061817992798
      Line 92, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

            Offending '(counter_lnt -> kmac_rom_vld_o)'
        UVM_ERROR @ 682963880 ps: (rom_ctrl_fsm.sv:317) [ASSERT FAILED] CounterLntImpliesKmacRomVldO_A
        UVM_INFO @ 682963880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---