ROM_CTRL/64KB Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	11.580s	228.294us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.540s	1.074ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.540s	537.415us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.120s	545.745us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.910s	1.343ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.840s	1.561ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.540s	537.415us	20	20	100.00
		rom_ctrl_csr_aliasing	10.910s	1.343ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.710s	301.143us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.450s	299.533us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	13.350s	1.542ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	52.090s	12.466ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	20.820s	1.424ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	16.030s	1.528ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.170s	1.999ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.170s	1.999ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.540s	1.074ms	5	5	100.00
		rom_ctrl_csr_rw	11.540s	537.415us	20	20	100.00
		rom_ctrl_csr_aliasing	10.910s	1.343ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.230s	549.438us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.540s	1.074ms	5	5	100.00
		rom_ctrl_csr_rw	11.540s	537.415us	20	20	100.00
		rom_ctrl_csr_aliasing	10.910s	1.343ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.230s	549.438us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	47.230s	9.565ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.454m	2.880ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.893m	1.249ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.454m	2.880ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.454m	2.880ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.454m	2.880ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.454m	2.880ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	11.580s	228.294us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	11.580s	228.294us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	11.580s	228.294us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.893m	1.249ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
		rom_ctrl_kmac_err_chk	20.820s	1.424ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.030m	2.663ms	3	20	15.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	47.230s	9.565ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.454m	2.880ms	5	5	100.00
V2S		TOTAL			48	65	73.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.652m	9.998ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			249	266	93.61

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.57	99.47	99.41	100.00	93.33	100.00	98.97	98.81

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 17 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 17 failures.

    • 1.rom_ctrl_corrupt_sig_fatal_chk.70647715910686197394645170412642487980611019545647508736148179664660166364293
      Line 75, in log /nightly/runs/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2497472879 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 2497472879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.rom_ctrl_corrupt_sig_fatal_chk.112033965169241573764274091036295929644564160942239925984190973310393980187216
      Line 94, in log /nightly/runs/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 17453657900 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 17453657900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 15 more failures.