RV_TIMER Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.220s	59.876us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.180s	18.844us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.200s	14.797us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.220s	279.025us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.310s	47.616us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.580s	40.866us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.200s	14.797us	20	20	100.00
		rv_timer_csr_aliasing	2.310s	47.616us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	2.390s	205.206us	20	20	100.00
V2	disabled	rv_timer_disabled	4.170s	4.143ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.931m	673.737ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.931m	673.737ms	10	10	100.00
V2	stress	rv_timer_stress_all	11.170s	4.178ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.250s	20.544us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.260s	281.247us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.270s	1.770ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.270s	1.770ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.180s	18.844us	5	5	100.00
		rv_timer_csr_rw	2.200s	14.797us	20	20	100.00
		rv_timer_csr_aliasing	2.310s	47.616us	5	5	100.00
		rv_timer_same_csr_outstanding	2.150s	39.992us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.180s	18.844us	5	5	100.00
		rv_timer_csr_rw	2.200s	14.797us	20	20	100.00
		rv_timer_csr_aliasing	2.310s	47.616us	5	5	100.00
		rv_timer_same_csr_outstanding	2.150s	39.992us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.130s	210.819us	5	5	100.00
		rv_timer_tl_intg_err	2.820s	606.261us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.820s	606.261us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.247m	9.014ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.000s	61.762us	10	10	100.00
		rv_timer_max	1.820s	42.671us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00