SPI_DEVICE/1R1W Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.728m	57.027ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.830s	131.074us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.410s	242.297us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.400s	1.862ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	27.270s	7.248ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.280s	670.632us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.410s	242.297us	20	20	100.00
		spi_device_csr_aliasing	27.270s	7.248ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.330s	25.890us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.300s	51.187us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.450s	17.150us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.320s	5.288us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.260s	5.429us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	9.380s	496.880us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.380s	496.880us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.590s	9.350ms	50	50	100.00
		spi_device_tpm_sts_read	2.770s	1.582ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.030m	10.806ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.290s	15.454ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.360s	155.172ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.360s	155.172ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.740s	4.605ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.740s	4.605ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.740s	4.605ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.740s	4.605ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.740s	4.605ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	56.260s	14.330ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.273m	15.462ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.273m	15.462ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.273m	15.462ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	44.880s	2.760ms	50	50	100.00
		spi_device_read_buffer_direct	17.440s	2.018ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.273m	15.462ms	50	50	100.00
		spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.190m	236.431ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.130s	6.603ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.130s	6.603ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.728m	57.027ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.616m	552.835ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.152m	123.940ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.400s	17.057us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.470s	108.734us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.710s	2.143ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.710s	2.143ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.830s	131.074us	5	5	100.00
		spi_device_csr_rw	4.410s	242.297us	20	20	100.00
		spi_device_csr_aliasing	27.270s	7.248ms	5	5	100.00
		spi_device_same_csr_outstanding	5.860s	399.183us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.830s	131.074us	5	5	100.00
		spi_device_csr_rw	4.410s	242.297us	20	20	100.00
		spi_device_csr_aliasing	27.270s	7.248ms	5	5	100.00
		spi_device_same_csr_outstanding	5.860s	399.183us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	3.090s	397.420us	5	5	100.00
		spi_device_tl_intg_err	20.410s	863.707us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.410s	863.707us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.462m	163.011ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.22	83.25	89.36	98.39	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.12863313034456945410650667903265455730002363749515438912437470231226454445196
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3341106 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[8])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3341106 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3341106 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[904])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.9251467293703062098930063806892294451685258064196071920128919510765712986725
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   9979284 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[39])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   9979284 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   9979284 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[935])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.105420115931055185238435346572467242076101715075619005266127036489932974538574
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4769692 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4769692 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   4819692 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7bcb11 [11110111100101100010001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4819692 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x7bcb11 [11110111100101100010001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])