SPI_DEVICE/2P Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.726m	89.980ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	4.620s	62.414us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	5.300s	40.108us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.050s	7.241ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.120s	1.231ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	6.010s	118.241us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	5.300s	40.108us	20	20	100.00
		spi_device_csr_aliasing	19.120s	1.231ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	4.140s	45.245us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	5.050s	60.090us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.410s	40.230us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.700s	28.893us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.820s	1.935us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.000s	590.624us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.000s	590.624us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.480s	16.742ms	50	50	100.00
		spi_device_tpm_sts_read	2.790s	153.683us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	38.220s	10.071ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.890s	25.738ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.950s	78.863ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.950s	78.863ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.320s	3.683ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.320s	3.683ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.320s	3.683ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.320s	3.683ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.320s	3.683ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	39.790s	15.428ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.989m	14.692ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.989m	14.692ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.989m	14.692ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	48.810s	5.257ms	50	50	100.00
		spi_device_read_buffer_direct	17.670s	1.271ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.989m	14.692ms	50	50	100.00
		spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.863m	258.857ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.380s	2.759ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.380s	2.759ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.726m	89.980ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.014m	297.085ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.751m	385.931ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.380s	108.962us	50	50	100.00
V2	intr_test	spi_device_intr_test	4.240s	12.476us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.870s	243.866us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.870s	243.866us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	4.620s	62.414us	5	5	100.00
		spi_device_csr_rw	5.300s	40.108us	20	20	100.00
		spi_device_csr_aliasing	19.120s	1.231ms	5	5	100.00
		spi_device_same_csr_outstanding	5.990s	802.610us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	4.620s	62.414us	5	5	100.00
		spi_device_csr_rw	5.300s	40.108us	20	20	100.00
		spi_device_csr_aliasing	19.120s	1.231ms	5	5	100.00
		spi_device_same_csr_outstanding	5.990s	802.610us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	2.240s	499.197us	5	5	100.00
		spi_device_tl_intg_err	20.840s	793.847us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.840s	793.847us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.613m	771.177ms	50	50	100.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.47	99.02	96.31	83.25	89.36	98.47	95.65	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.90350950971461015603054278128217085750128714015391446481106892932540913776503
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    894561 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    894561 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    982561 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x622af5 [11000100010101011110101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    982561 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)