SPI_HOST Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.950m	12.539ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	26.114us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	18.162us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	212.211us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	29.241us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	40.374us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	18.162us	20	20	100.00
		spi_host_csr_aliasing	5.000s	29.241us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	20.829us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	32.697us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	6.000s	161.513us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	33.000s	565.171us	50	50	100.00
		spi_host_error_cmd	5.000s	23.565us	50	50	100.00
		spi_host_event	15.333m	26.233ms	50	50	100.00
V2	clock_rate	spi_host_speed	10.000s	187.601us	50	50	100.00
V2	speed	spi_host_speed	10.000s	187.601us	50	50	100.00
V2	chip_select_timing	spi_host_speed	10.000s	187.601us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.900m	16.262ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	133.389us	50	50	100.00
V2	cpol_cpha	spi_host_speed	10.000s	187.601us	50	50	100.00
V2	full_cycle	spi_host_speed	10.000s	187.601us	50	50	100.00
V2	duplex	spi_host_smoke	1.950m	12.539ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	1.950m	12.539ms	49	50	98.00
V2	stress_all	spi_host_stress_all	2.000m	19.032ms	50	50	100.00
V2	spien	spi_host_spien	1.583m	20.557ms	50	50	100.00
V2	stall	spi_host_status_stall	10.500m	62.630ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	31.000s	16.889ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	33.000s	565.171us	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	51.439us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	57.967us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	69.436us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	69.436us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	26.114us	5	5	100.00
		spi_host_csr_rw	5.000s	18.162us	20	20	100.00
		spi_host_csr_aliasing	5.000s	29.241us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	66.719us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	26.114us	5	5	100.00
		spi_host_csr_rw	5.000s	18.162us	20	20	100.00
		spi_host_csr_aliasing	5.000s	29.241us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	66.719us	20	20	100.00
V2		TOTAL			690	690	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	166.057us	20	20	100.00
		spi_host_sec_cm	5.000s	74.961us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	166.057us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	11.000m	183.576ms	9	10	90.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.31	96.78	93.27	98.69	94.47	88.02	100.00	97.27	91.56

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 7.spi_host_upper_range_clkdiv.46270323456786752303479993785280655279928655042218775441700013695759979039707
      Line 158, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_smoke has 1 failures.

    • 30.spi_host_smoke.48539016685609109818846942335601975319263922869468783458811745888206376234440
      Line 164, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/30.spi_host_smoke/latest/run.log

        UVM_FATAL @ 15063284980 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0x29929854, Comparison=CompareOpEq, exp_data=0x0, call_count=18
        UVM_INFO @ 15063284980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---