SRAM_CTRL/MAIN Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.537m	941.182us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.200s	39.810us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.370s	43.200us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	4.280s	1.610ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.260s	11.834us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.730s	1.449ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.370s	43.200us	20	20	100.00
		sram_ctrl_csr_aliasing	2.260s	11.834us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.042m	66.736ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.365m	8.923ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.854m	25.914ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.994m	5.883ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.555m	168.838ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.002m	168.654ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.048m	20.787ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.810m	34.270ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.786m	5.908ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.709m	126.777ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.859m	3.464ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.883m	1.590ms	50	50	100.00
		sram_ctrl_throughput_w_readback	2.099m	977.275us	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.011m	77.821ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.490s	3.752ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.404h	1.840s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.140s	119.135us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.300s	599.585us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.300s	599.585us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.200s	39.810us	5	5	100.00
		sram_ctrl_csr_rw	2.370s	43.200us	20	20	100.00
		sram_ctrl_csr_aliasing	2.260s	11.834us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.550s	26.579us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.200s	39.810us	5	5	100.00
		sram_ctrl_csr_rw	2.370s	43.200us	20	20	100.00
		sram_ctrl_csr_aliasing	2.260s	11.834us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.550s	26.579us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.078m	37.010ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.100s	11.909us	0	5	0.00
		sram_ctrl_tl_intg_err	4.930s	325.728us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.100s	11.909us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.930s	325.728us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.011m	77.821ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.011m	77.821ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.370s	43.200us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.810m	34.270ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.810m	34.270ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.810m	34.270ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.048m	20.787ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.120s	5.522ms	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.078m	37.010ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.920s	4.770ms	38	50	76.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.537m	941.182us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.537m	941.182us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.810m	34.270ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.100s	11.909us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.048m	20.787ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.100s	11.909us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.100s	11.909us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.537m	941.182us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.100s	11.909us	0	5	0.00
V2S		TOTAL			119	145	82.07
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.983m	14.404ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 12 failures:

  • Test sram_ctrl_readback_err has 12 failures.

    • 0.sram_ctrl_readback_err.113708178516796344751096232150850086781034925746212861001515160856710974927993
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 4381547458 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5f) != exp (0x12)
        UVM_INFO @ 4381547458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_readback_err.84792882597982143064446927580707281610472253637870207112900217091420911935491
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 724920279 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x69) != exp (0x26)
        UVM_INFO @ 724920279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 10 more failures.

• Offending 'reqfifo_rvalid' has 8 failures:

  • Test sram_ctrl_mubi_enc_err has 8 failures.

    • 0.sram_ctrl_mubi_enc_err.86877036787400462594886514680682201403973366150844950846245953107987999076670
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1356080938 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1356080938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 13.sram_ctrl_mubi_enc_err.45093219686910795668167677246037884282349329052716375746702090650769882537264
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/13.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2857118401 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2857118401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.35335026669994387966400290935772577132699993600380204740967571580482365944590
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  21278318 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  21278318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.76551331446229564019013051650370617282041348838224373375666722155888076608420
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4234755 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4234755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.37181424967405167833653652484121589697024762152719831297606727685725875192555
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4281890 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4281890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_tl_intg_err has 1 failures.

    • 18.sram_ctrl_tl_intg_err.5337242513441478076126201348230622485095431190772467080342988076153427038518
      Line 383, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 467357877 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 467357877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---