SRAM_CTRL/RET Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.763m	2.503ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.000s	15.747us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.180s	16.184us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.330s	509.691us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.060s	11.737us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.110s	137.845us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.180s	16.184us	20	20	100.00
		sram_ctrl_csr_aliasing	2.060s	11.737us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.700s	1.962ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.380s	381.623us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	22.774m	17.590ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.625m	20.612ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.430m	67.205ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.959m	9.476ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.780s	1.656ms	49	50	98.00
V2	executable	sram_ctrl_executable	27.843m	99.140ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.770m	227.084us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.766m	20.428ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.590m	652.356us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.696m	150.974us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.823m	2.945ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.730m	26.753ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.350s	46.362us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.102h	257.599ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.130s	42.131us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.990s	488.702us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.990s	488.702us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.000s	15.747us	5	5	100.00
		sram_ctrl_csr_rw	2.180s	16.184us	20	20	100.00
		sram_ctrl_csr_aliasing	2.060s	11.737us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.070s	87.166us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.000s	15.747us	5	5	100.00
		sram_ctrl_csr_rw	2.180s	16.184us	20	20	100.00
		sram_ctrl_csr_aliasing	2.060s	11.737us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.070s	87.166us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.850s	2.700ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.030s	19.770us	0	5	0.00
		sram_ctrl_tl_intg_err	3.970s	177.187us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.030s	19.770us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.970s	177.187us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.730m	26.753ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.730m	26.753ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.180s	16.184us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.843m	99.140ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.843m	99.140ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.843m	99.140ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.780s	1.656ms	49	50	98.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.630s	47.788us	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.850s	2.700ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.640s	79.686us	38	50	76.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.763m	2.503ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.763m	2.503ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.843m	99.140ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.030s	19.770us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.780s	1.656ms	49	50	98.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.030s	19.770us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.030s	19.770us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.763m	2.503ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.030s	19.770us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.203m	6.379ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1163	1190	97.73

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	99.26	93.01	85.10	100.00	97.99	98.58	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 12 failures:

  • Test sram_ctrl_readback_err has 12 failures.

    • 7.sram_ctrl_readback_err.57969353010595851748883335994031084401963496959417941219365464381495506129290
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23924699 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5d) != exp (0xc)
        UVM_INFO @  23924699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_readback_err.10248021517193175737981393632104222272659015524864232295131129009420009266948
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  33201110 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x13) != exp (0x2d)
        UVM_INFO @  33201110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 10 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:

  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 0.sram_ctrl_mubi_enc_err.69811764969078308912841485298196268815249749666229708702957601267047493951843
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 311660919 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 311660919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.sram_ctrl_mubi_enc_err.55961021858046569089061860539036863087882809403353009786102369036841132440701
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  24882647 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  24882647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 1.sram_ctrl_sec_cm.15375724521441955306988639724573873599006450794574831288422334869105323677530
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1824049 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1824049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.8879463782748449832251390864278058141036832338542639007410813708285292953529
      Line 102, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7027462 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7027462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 3 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 3 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.72092237636011242190359965289849807408807943131635877484207802545455453586190
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 129278379 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 129278379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_csr_mem_rw_with_rand_reset.58149643690097848076654142504290654675006985659442440476929979343161064351786
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 223843387 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 223843387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.6157031853197994359092572950790409643697223303507853997755757424143497838855
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3939864 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3939864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_tl_intg_err has 1 failures.

    • 10.sram_ctrl_tl_intg_err.57781516630378448020473480016452824442478970251955893364023679022538511386301
      Line 152, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @  74591976 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @  74591976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test sram_ctrl_lc_escalation has 1 failures.

    • 16.sram_ctrl_lc_escalation.6174538808699277951912747982679620265815090914905039538293923115825598184482
      Line 91, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest/run.log

        UVM_ERROR @ 530023887 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0xd0 [11010000] vs 0x23 [100011]) addr 0xebe34ec read out mismatch
        UVM_INFO @ 530023887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:832) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.sram_ctrl_stress_all_with_rand_reset.23881805345004766310090671691543619217546617479004121657939925975881066450578
      Line 168, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2722840324 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2722840324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---