UART Simulation Results

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	39.810s	6.069ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.080s	26.630us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.260s	39.765us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.450s	649.269us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.340s	27.376us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.450s	159.477us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.260s	39.765us	20	20	100.00
		uart_csr_aliasing	2.340s	27.376us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.554m	122.959ms	50	50	100.00
V2	parity	uart_smoke	39.810s	6.069ms	50	50	100.00
		uart_tx_rx	4.554m	122.959ms	50	50	100.00
V2	parity_error	uart_intr	10.760m	385.848ms	50	50	100.00
		uart_rx_parity_err	6.217m	172.757ms	50	50	100.00
V2	watermark	uart_tx_rx	4.554m	122.959ms	50	50	100.00
		uart_intr	10.760m	385.848ms	50	50	100.00
V2	fifo_full	uart_fifo_full	14.140m	215.398ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.428m	74.314ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	14.761m	162.156ms	298	300	99.33
V2	rx_frame_err	uart_intr	10.760m	385.848ms	50	50	100.00
V2	rx_break_err	uart_intr	10.760m	385.848ms	50	50	100.00
V2	rx_timeout	uart_intr	10.760m	385.848ms	50	50	100.00
V2	perf	uart_perf	14.476m	21.650ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.050s	6.497ms	50	50	100.00
V2	line_loopback	uart_loopback	25.050s	6.497ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.675m	156.309ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.619m	72.143ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	29.750s	12.957ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.132m	6.673ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.360m	150.897ms	49	50	98.00
V2	stress_all	uart_stress_all	27.817m	817.358ms	50	50	100.00
V2	alert_test	uart_alert_test	2.140s	19.517us	50	50	100.00
V2	intr_test	uart_intr_test	2.230s	49.604us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.720s	1.976ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.720s	1.976ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.080s	26.630us	5	5	100.00
		uart_csr_rw	2.260s	39.765us	20	20	100.00
		uart_csr_aliasing	2.340s	27.376us	5	5	100.00
		uart_same_csr_outstanding	2.350s	29.453us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.080s	26.630us	5	5	100.00
		uart_csr_rw	2.260s	39.765us	20	20	100.00
		uart_csr_aliasing	2.340s	27.376us	5	5	100.00
		uart_same_csr_outstanding	2.350s	29.453us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	2.350s	120.805us	5	5	100.00
		uart_tl_intg_err	2.950s	97.038us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.950s	97.038us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.657m	16.856ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1312	1320	99.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.17	98.25	91.55	--	98.14	100.00	99.48

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 4 failures:

  • Test uart_fifo_overflow has 1 failures.

    • 2.uart_fifo_overflow.59736886369831145922544596479374894707025872725359453740945918115474246890318
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/2.uart_fifo_overflow/latest/run.log

        UVM_ERROR @ 11343457140 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 23203506234 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/10
        UVM_INFO @ 24424439212 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/10
        UVM_INFO @ 27580706458 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 5/10
        UVM_INFO @ 28898666650 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 6/10
      

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 36.uart_long_xfer_wo_dly.22876928668556077252045966402240113117469565695344823137563911734776580431899
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @   4768593 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 33523958781 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
        UVM_INFO @ 42247862959 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/5
        UVM_INFO @ 72872635731 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/5
        UVM_INFO @ 80996413075 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/5
      

  • Test uart_fifo_reset has 2 failures.

    • 266.uart_fifo_reset.9858016308933189319127628813017553061070147920659897437937170603235326804465
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/266.uart_fifo_reset/latest/run.log

        UVM_ERROR @ 42082855147 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 45805797194 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
        UVM_INFO @ 45855705041 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
        UVM_INFO @ 46031669005 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
        UVM_INFO @ 46237675597 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8
      

    • 290.uart_fifo_reset.59265926553954842111863595727528635474462044557102663367184376235539288025670
      Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/290.uart_fifo_reset/latest/run.log

        UVM_ERROR @ 39275384436 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 102511263849 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
        UVM_INFO @ 103099767380 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
        UVM_INFO @ 103205839445 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8
        UVM_INFO @ 104532775978 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/8
      

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:

  • Test uart_stress_all_with_rand_reset has 3 failures.

    • 16.uart_stress_all_with_rand_reset.84962009811698446968677500622357190759925120331523790000808198064306213118856
      Line 82, in log /nightly/runs/scratch/master/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2294727025 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2294727025 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 2/10
        UVM_INFO @ 2294810359 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 2/10
      

    • 45.uart_stress_all_with_rand_reset.22935308953582584934109718983794221851204679361661311705674575809343288734159
      Line 163, in log /nightly/runs/scratch/master/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11670722109 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 11670722109 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 9/10
        UVM_INFO @ 11671013778 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 9/10
      

    • ... and 1 more failures.

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 68.uart_stress_all_with_rand_reset.26136914973517926719952349766587945785008260845354819449807073023740981568276
      Line 178, in log /nightly/runs/scratch/master/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1997920812 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
        UVM_INFO @ 2006383394 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 10/10
        UVM_INFO @ 2006476175 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 10/10