ADC_CTRL Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.460s	6.124ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	5.680s	1.227ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.520s	543.255us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.324m	25.813ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.610s	1.400ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.430s	349.904us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.520s	543.255us	20	20	100.00
		adc_ctrl_csr_aliasing	4.610s	1.400ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	22.277m	496.259ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.341m	501.246ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	18.575m	484.448ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	23.104m	490.659ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.632m	526.138ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.684m	598.364ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.474m	586.437ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	14.030m	447.147ms	35	50	70.00
V2	poweron_counter	adc_ctrl_poweron_counter	19.810s	5.544ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.397m	43.287ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	7.688m	130.474ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.759m	649.731ms	49	50	98.00
V2	alert_test	adc_ctrl_alert_test	3.690s	510.541us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.790s	469.121us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.940s	522.738us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.940s	522.738us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	5.680s	1.227ms	5	5	100.00
		adc_ctrl_csr_rw	3.520s	543.255us	20	20	100.00
		adc_ctrl_csr_aliasing	4.610s	1.400ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.440s	4.012ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	5.680s	1.227ms	5	5	100.00
		adc_ctrl_csr_rw	3.520s	543.255us	20	20	100.00
		adc_ctrl_csr_aliasing	4.610s	1.400ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.440s	4.012ms	20	20	100.00
V2		TOTAL			723	740	97.70
V2S	tl_intg_err	adc_ctrl_sec_cm	29.470s	7.436ms	5	5	100.00
		adc_ctrl_tl_intg_err	19.600s	8.455ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	19.600s	8.455ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.578m	10.000s	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			899	920	97.72

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.65	99.11	96.45	100.00	100.00	99.01	98.06	90.96

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:

  • Test adc_ctrl_clock_gating has 11 failures.

    • 0.adc_ctrl_clock_gating.57816423919848942996725085251505581091971619095158446328269343818330897582951
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.adc_ctrl_clock_gating.77804533419194953964434127086752886347643901743276045922727944340474021522854
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

  • Test adc_ctrl_stress_all has 1 failures.

    • 6.adc_ctrl_stress_all.107614123243259166603932172479464000304012732511324874543874987985465624599429
      Line 166, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.adc_ctrl_stress_all_with_rand_reset.42404023462458197246585629978767258511493759898724647389862908497010335027545
      Line 156, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 26.adc_ctrl_stress_all_with_rand_reset.48614090917445239943220698302639699664614333635716257284236073317676470098183
      Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_filters_both has 1 failures.

    • 21.adc_ctrl_filters_both.102263645186876732142675004095157313633635306806971587810990554015071824247574
      Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 6 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 19.adc_ctrl_stress_all_with_rand_reset.70759693329966576248578296470180633984049586305415762051490464973455089253752
      Line 200, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4719260135 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 4719260135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 39.adc_ctrl_stress_all_with_rand_reset.5293010538911866058986852558047709363836344635454728523637230152728988123037
      Line 173, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3541930401 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 3541930401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_clock_gating has 4 failures.

    • 22.adc_ctrl_clock_gating.23553746141178292403442712839542486800174422071012339678321925848999978984143
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 1522515374 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 1522515374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 30.adc_ctrl_clock_gating.96135361467107621507417300655015476389414920063804380665466691726032367333748
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 13858358417 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 13858358417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.