AES/MASKED Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	20.000s	72.427us	1	1	100.00
V1	smoke	aes_smoke	21.000s	106.595us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	58.611us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	55.974us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.993ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	196.616us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	94.436us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	55.974us	20	20	100.00
		aes_csr_aliasing	6.000s	196.616us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	21.000s	106.595us	50	50	100.00
		aes_config_error	21.000s	80.142us	50	50	100.00
		aes_stress	23.000s	148.247us	50	50	100.00
V2	key_length	aes_smoke	21.000s	106.595us	50	50	100.00
		aes_config_error	21.000s	80.142us	50	50	100.00
		aes_stress	23.000s	148.247us	50	50	100.00
V2	back2back	aes_stress	23.000s	148.247us	50	50	100.00
		aes_b2b	27.000s	452.157us	50	50	100.00
V2	backpressure	aes_stress	23.000s	148.247us	50	50	100.00
V2	multi_message	aes_smoke	21.000s	106.595us	50	50	100.00
		aes_config_error	21.000s	80.142us	50	50	100.00
		aes_stress	23.000s	148.247us	50	50	100.00
		aes_alert_reset	21.000s	285.672us	50	50	100.00
V2	failure_test	aes_man_cfg_err	20.000s	58.466us	50	50	100.00
		aes_config_error	21.000s	80.142us	50	50	100.00
		aes_alert_reset	21.000s	285.672us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.017m	7.229ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	26.000s	540.224us	1	1	100.00
V2	reset_recovery	aes_alert_reset	21.000s	285.672us	50	50	100.00
V2	stress	aes_stress	23.000s	148.247us	50	50	100.00
V2	sideload	aes_stress	23.000s	148.247us	50	50	100.00
		aes_sideload	23.000s	304.464us	50	50	100.00
V2	deinitialization	aes_deinit	34.000s	2.184ms	50	50	100.00
V2	stress_all	aes_stress_all	1.417m	69.555ms	10	10	100.00
V2	alert_test	aes_alert_test	19.000s	80.531us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	833.723us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	833.723us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	58.611us	5	5	100.00
		aes_csr_rw	5.000s	55.974us	20	20	100.00
		aes_csr_aliasing	6.000s	196.616us	5	5	100.00
		aes_same_csr_outstanding	6.000s	494.110us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	58.611us	5	5	100.00
		aes_csr_rw	5.000s	55.974us	20	20	100.00
		aes_csr_aliasing	6.000s	196.616us	5	5	100.00
		aes_same_csr_outstanding	6.000s	494.110us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	23.000s	658.829us	50	50	100.00
V2S	fault_inject	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	376.282us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	376.282us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	376.282us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	376.282us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	162.153us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	20.000s	370.949us	5	5	100.00
		aes_tl_intg_err	6.000s	180.185us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	180.185us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	21.000s	285.672us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	376.282us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	21.000s	106.595us	50	50	100.00
		aes_stress	23.000s	148.247us	50	50	100.00
		aes_alert_reset	21.000s	285.672us	50	50	100.00
		aes_core_fi	42.000s	10.010ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	376.282us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	20.000s	104.521us	50	50	100.00
		aes_stress	23.000s	148.247us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	23.000s	148.247us	50	50	100.00
		aes_sideload	23.000s	304.464us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	20.000s	104.521us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	20.000s	104.521us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	20.000s	104.521us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	20.000s	104.521us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	20.000s	104.521us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	23.000s	148.247us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	23.000s	148.247us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	30.000s	2.543ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
		aes_ctr_fi	19.000s	84.804us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	30.000s	2.543ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.003ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	30.000s	2.543ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_ctr_fi	19.000s	84.804us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
		aes_ctr_fi	19.000s	84.804us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	21.000s	285.672us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
		aes_ctr_fi	19.000s	84.804us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
		aes_ctr_fi	19.000s	84.804us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_ctr_fi	19.000s	84.804us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	30.000s	2.543ms	49	50	98.00
		aes_control_fi	41.000s	10.243ms	287	300	95.67
		aes_cipher_fi	46.000s	10.003ms	341	350	97.43
V2S		TOTAL			960	985	97.46
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	5.220ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1567	1602	97.82

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.43	98.64	96.54	99.45	95.70	97.99	97.78	98.96	98.99

Failure Buckets

Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 9 failures.
  - 43.aes_control_fi.29741546134310887166082615896953063472419812924335310112024729434285819563115
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 103.aes_control_fi.34580157202029202798403500566012306685815828380469573007982562197212974986971
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/103.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 54.aes_cipher_fi.101555897927820454825872153673462317547723230566176703468002279500382789046225
    Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005365054 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005365054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 66.aes_cipher_fi.100749356182766082263260505509732293806356159005369773682656551189297169153171
    Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003083303 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003083303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

3.aes_stress_all_with_rand_reset.52739229418710958344804786207504435609228777041298381255345073310454123809142
Line 203, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 138249572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 138249572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.92503131880506190422714859126858337645805385127185872546222970323990346484107
Line 375, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 257085830 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 257085830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 32.aes_control_fi.28118201611003728903275836402442890129230280057721862180950839722328297661990
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10032336991 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032336991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.aes_control_fi.58547072215986221428807680380317507124415368726192377178385098691411606793489
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004077222 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004077222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.48498812444910621493064126896362567856647999241021211695409381585139731948745
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008449782 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008449782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 30.aes_core_fi.71868229591987665944303452098608395575038958853464656200283576304544139932130
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010020226 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010020226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.22116748129682904779782997069133400184424458743396635318605791083546565494562
    Line 352, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 990079542 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 990079542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.90735404710680181857596253457980314395920322260184450437954763916050027624583
    Line 154, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 510332375 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 510332375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.31986292431255007511119638403735864688485726432473865128784524778615064803823
    Line 171, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 204818992 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 204818992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 23.aes_fi.80792099049730634739426986358076112820448890855605654259112491063718813718578
    Line 25585, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/23.aes_fi/latest/run.log
```
  UVM_FATAL @ 233653937 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 233653937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```