AES/UNMASKED Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	10.000s	91.389us	1	1	100.00
V1	smoke	aes_smoke	7.000s	62.002us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	78.738us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	54.772us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	842.004us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	299.531us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	190.384us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	54.772us	20	20	100.00
		aes_csr_aliasing	6.000s	299.531us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	62.002us	50	50	100.00
		aes_config_error	7.000s	94.154us	50	50	100.00
		aes_stress	7.000s	122.010us	50	50	100.00
V2	key_length	aes_smoke	7.000s	62.002us	50	50	100.00
		aes_config_error	7.000s	94.154us	50	50	100.00
		aes_stress	7.000s	122.010us	50	50	100.00
V2	back2back	aes_stress	7.000s	122.010us	50	50	100.00
		aes_b2b	12.000s	219.563us	50	50	100.00
V2	backpressure	aes_stress	7.000s	122.010us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	62.002us	50	50	100.00
		aes_config_error	7.000s	94.154us	50	50	100.00
		aes_stress	7.000s	122.010us	50	50	100.00
		aes_alert_reset	6.000s	81.866us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	137.118us	50	50	100.00
		aes_config_error	7.000s	94.154us	50	50	100.00
		aes_alert_reset	6.000s	81.866us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	369.959us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	308.554us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	81.866us	50	50	100.00
V2	stress	aes_stress	7.000s	122.010us	50	50	100.00
V2	sideload	aes_stress	7.000s	122.010us	50	50	100.00
		aes_sideload	6.000s	65.708us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	264.170us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	3.243ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	67.268us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	1.018ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	1.018ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	78.738us	5	5	100.00
		aes_csr_rw	5.000s	54.772us	20	20	100.00
		aes_csr_aliasing	6.000s	299.531us	5	5	100.00
		aes_same_csr_outstanding	6.000s	158.578us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	78.738us	5	5	100.00
		aes_csr_rw	5.000s	54.772us	20	20	100.00
		aes_csr_aliasing	6.000s	299.531us	5	5	100.00
		aes_same_csr_outstanding	6.000s	158.578us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	742.205us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	209.024us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	209.024us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	209.024us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	209.024us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	317.909us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	4.794ms	5	5	100.00
		aes_tl_intg_err	7.000s	927.031us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	927.031us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	81.866us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	209.024us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	62.002us	50	50	100.00
		aes_stress	7.000s	122.010us	50	50	100.00
		aes_alert_reset	6.000s	81.866us	50	50	100.00
		aes_core_fi	1.483m	10.015ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	209.024us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	57.910us	50	50	100.00
		aes_stress	7.000s	122.010us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	122.010us	50	50	100.00
		aes_sideload	6.000s	65.708us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	57.910us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	57.910us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	57.910us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	57.910us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	57.910us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	122.010us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	122.010us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	151.547us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
		aes_ctr_fi	6.000s	205.375us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	151.547us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.006ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	151.547us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_ctr_fi	6.000s	205.375us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
		aes_ctr_fi	6.000s	205.375us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	81.866us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
		aes_ctr_fi	6.000s	205.375us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
		aes_ctr_fi	6.000s	205.375us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_ctr_fi	6.000s	205.375us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	151.547us	49	50	98.00
		aes_control_fi	41.000s	200.000ms	277	300	92.33
		aes_cipher_fi	32.000s	10.006ms	324	350	92.57
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	34.000s	2.708ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.32	97.67	94.75	98.84	93.54	97.99	93.33	98.65	97.59

Failure Buckets

Job timed out after * minutes has 25 failures:
- Test aes_cipher_fi has 15 failures.
  - 25.aes_cipher_fi.81656980828493842320256737310153479072453776611675269323696485789414926424441
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 30.aes_cipher_fi.17155631499529167772312427468689001766297110993311458876541844872750805561465
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
- Test aes_control_fi has 10 failures.
  - 58.aes_control_fi.64736771534429486037748601582216932715018752368987234008995912676786331894213
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 92.aes_control_fi.77301742781143718757500955390551826298936056829035134009587577439050073674886
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/92.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 11.aes_control_fi.25621115660118689577681703865905173790506216508078881146909740444581110496700
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012179389 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012179389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 34.aes_control_fi.110798430031311487622766250111986478573474748721519766917201782897946896228983
    Line 146, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011269531 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011269531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 40.aes_cipher_fi.1023002073461366774730436411670106001195194827784610132714828750368990449923
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10055210816 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10055210816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 54.aes_cipher_fi.24344882535882997222827608713625688335845934971002477303585670549047588128660
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006057968 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006057968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.74836489680393156465603243510823516571872530854100467385299447966777004316768
Line 1792, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1633444488 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1633444488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.53908116596407653995394101974049405673531995867372275322230580157055744504645
Line 1082, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 768056956 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 768056956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.42142848864489597373007731406347496524947129918282411072285871095680322327299
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10048479105 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048479105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.aes_core_fi.29445213100372310177259502966321056142947430395386611602956003896258352314586
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023050559 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023050559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 27.aes_core_fi.25849593129869497693893119582260387651683140099044181128586938229480058875863
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016577568 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016577568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.aes_core_fi.55751343942073240097111789402331091822699616004581292603026998523871878732202
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004048537 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004048537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.63196400513571046531106264873683432574163831984181525523969984388729068898843
    Line 172, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  18632167 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  18632167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 9.aes_core_fi.41379919949141685756135047440040077364681369131832388786553722091560993812475
    Line 130, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014855572 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xe31f9a84, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10014855572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.71150558971417074210501538513756976385293831176316281198776503421056117420067
    Line 489, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 460018494 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 460018494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

23.aes_fi.107520099114429306738134085764734063014877109193279743986579689137877210005903
Line 1199, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 75841648 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 75774981 PS)
  UVM_ERROR @  75841648 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  75841648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 33.aes_control_fi.39060644684601765133302836129171794230627694133540630018027453152188146650235
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_control_fi has 1 failures.

264.aes_control_fi.18933646665931038454951542800403137720812641868990472467635313017373738997878
Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/264.aes_control_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 57737617 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 57692162 PS)
  UVM_ERROR @  57737617 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  57737617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---