AON_TIMER Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.910s	557.923us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.420s	1.057ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.600s	411.228us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	8.650s	14.067ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.470s	527.010us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.840s	507.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.600s	411.228us	20	20	100.00
		aon_timer_csr_aliasing	2.470s	527.010us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.380s	417.215us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.070s	505.797us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	52.260s	38.975ms	15	15	100.00
V2	jump	aon_timer_jump	3.310s	739.381us	5	5	100.00
V2	stress_all	aon_timer_stress_all	2.048m	87.235ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	3.150s	469.391us	50	50	100.00
V2	intr_test	aon_timer_intr_test	2.850s	367.122us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.730s	874.766us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.730s	874.766us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.420s	1.057ms	5	5	100.00
		aon_timer_csr_rw	2.600s	411.228us	20	20	100.00
		aon_timer_csr_aliasing	2.470s	527.010us	5	5	100.00
		aon_timer_same_csr_outstanding	6.720s	2.268ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.420s	1.057ms	5	5	100.00
		aon_timer_csr_rw	2.600s	411.228us	20	20	100.00
		aon_timer_csr_aliasing	2.470s	527.010us	5	5	100.00
		aon_timer_same_csr_outstanding	6.720s	2.268ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	17.510s	7.393ms	5	5	100.00
		aon_timer_tl_intg_err	12.450s	8.333ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.450s	8.333ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	3.020s	621.125us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	3.040s	696.510us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	13.530s	3.348ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	2.940s	648.415us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	18.290s	4.231ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	47.400s	21.825ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00