CSRNG Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	226.791us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	107.925us	5	5	100.00
V1	csr_rw	csrng_csr_rw	11.000s	30.190us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	22.000s	521.219us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	463.102us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	13.000s	81.707us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	11.000s	30.190us	20	20	100.00
		csrng_csr_aliasing	11.000s	463.102us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	979.636us	199	200	99.50
V2	alerts	csrng_alert	1.450m	6.078ms	500	500	100.00
V2	err	csrng_err	7.000s	20.916us	500	500	100.00
V2	cmds	csrng_cmds	12.800m	73.328ms	50	50	100.00
V2	life cycle	csrng_cmds	12.800m	73.328ms	50	50	100.00
V2	stress_all	csrng_stress_all	33.183m	187.579ms	45	50	90.00
V2	intr_test	csrng_intr_test	22.000s	118.334us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	334.652us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	35.000s	2.560ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	35.000s	2.560ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	107.925us	5	5	100.00
		csrng_csr_rw	11.000s	30.190us	20	20	100.00
		csrng_csr_aliasing	11.000s	463.102us	5	5	100.00
		csrng_same_csr_outstanding	15.000s	193.243us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	107.925us	5	5	100.00
		csrng_csr_rw	11.000s	30.190us	20	20	100.00
		csrng_csr_aliasing	11.000s	463.102us	5	5	100.00
		csrng_same_csr_outstanding	15.000s	193.243us	20	20	100.00
V2		TOTAL			1434	1440	99.58
V2S	tl_intg_err	csrng_sec_cm	9.000s	148.596us	5	5	100.00
		csrng_tl_intg_err	16.000s	494.528us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	134.784us	50	50	100.00
		csrng_csr_rw	11.000s	30.190us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.450m	6.078ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	33.183m	187.579ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.450m	6.078ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	33.183m	187.579ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.450m	6.078ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	494.528us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
		csrng_sec_cm	9.000s	148.596us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	979.636us	199	200	99.50
		csrng_err	7.000s	20.916us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.000m	1.746ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1614	1630	99.02

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.73	98.61	96.62	99.94	97.36	92.15	100.00	97.36	90.36

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.60089755127238142711981628810145549914825414397189891925258711505522039870658
      Line 103, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3072412757 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3072412757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.30406768145569567436168773521245574263228308341171593344392884484359022001816
      Line 101, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 876581967 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 876581967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:
  • Test csrng_stress_all has 5 failures.

    • 2.csrng_stress_all.78158041135278112019010106434764131798495377255145050503213751963200827904820
      Line 147, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log

        UVM_ERROR @ 6243710084 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 6243710084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.csrng_stress_all.45459326342778945062862065999135418815794604192464382174526121849941889571682
      Line 131, in log /nightly/runs/scratch/master/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log

        UVM_ERROR @  21995670 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  21995670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:
  • Test csrng_intr has 1 failures.

    • 43.csrng_intr.65928119147825646807956021271053017214522938891428076528734210042797163954458
      Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/43.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 60932343 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @  60932343 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @  60932343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---