EDN Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.640s 18.353us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.280s 26.473us 5 5 100.00
V1 csr_rw edn_csr_rw 2.510s 17.308us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.570s 507.044us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.350s 24.714us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.570s 25.556us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.510s 17.308us 20 20 100.00
edn_csr_aliasing 2.350s 24.714us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 7.230s 691.441us 300 300 100.00
V2 csrng_commands edn_genbits 7.230s 691.441us 300 300 100.00
V2 genbits edn_genbits 7.230s 691.441us 300 300 100.00
V2 interrupts edn_intr 2.690s 20.884us 50 50 100.00
V2 alerts edn_alert 3.200s 26.687us 200 200 100.00
V2 errs edn_err 2.890s 28.868us 100 100 100.00
V2 disable edn_disable 2.430s 12.024us 50 50 100.00
edn_disable_auto_req_mode 3.160s 51.418us 50 50 100.00
V2 stress_all edn_stress_all 8.740s 676.777us 50 50 100.00
V2 intr_test edn_intr_test 2.450s 16.248us 50 50 100.00
V2 alert_test edn_alert_test 2.500s 73.799us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.070s 239.088us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.070s 239.088us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.280s 26.473us 5 5 100.00
edn_csr_rw 2.510s 17.308us 20 20 100.00
edn_csr_aliasing 2.350s 24.714us 5 5 100.00
edn_same_csr_outstanding 2.710s 41.664us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.280s 26.473us 5 5 100.00
edn_csr_rw 2.510s 17.308us 20 20 100.00
edn_csr_aliasing 2.350s 24.714us 5 5 100.00
edn_same_csr_outstanding 2.710s 41.664us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 11.070s 614.541us 5 5 100.00
edn_tl_intg_err 3.790s 162.465us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.450s 19.413us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.200s 26.687us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 11.070s 614.541us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 11.070s 614.541us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 11.070s 614.541us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 11.070s 614.541us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.200s 26.687us 200 200 100.00
edn_sec_cm 11.070s 614.541us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.200s 26.687us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.790s 162.465us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.026m 5.772ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.94 98.32 94.29 97.07 93.02 96.33 99.78 92.75

Failure Buckets